Maarten Debucquoy

Correlation between bias stress instability and phototransistor operation of pentacene thin-film transistors

The authors study the use of pentacene thin-film transistors as phototransistors. The shift in turn-on voltage (Von), responsible for the high photosensitivity of these devices, is shown to be strongly dependent on illumination time and applied gate voltage. The time dependence of this process is similar to the shift in Von during bias stress experiments in the dark, and illumination can simply be accounted for as an acceleration factor for bias stress instability. By comparing the characteristics of devices with different gate dielectrics, trapping of electrons by OH groups at the gate dielectric interface is indicated as a main origin for these shifts.

Noise-Margin Analysis for Organic Thin-Film Complementary Technology

Parameter variation in organic thin-film transistor (OTFT) technology is known to limit the yield of digital circuits. It is expected that complementary OTFT technology (C-TFT) will reduce the sensitivity to parameter variations. In this paper, we quantify the dependence of yield on transistor parameter variations for C-TFT and compare it to unipolar logic. First, a basic inverter model is developed and fitted to measured transfer characteristics of organic complementary inverters. Next, the inverter model is used in numerical simulations to determine how the noise margin of the inverter, a measure for its reliable operation, changes as a function of transistor parameter variations. The noise margin is significantly improved with respect to p-type-only inverters with similar parameters. Finally, we perform circuit-level yield predictions as a function of parameter spread using the noise-margin simulations performed earlier.

Numerical simulation of tetracene light-emitting transistors: A detailed balance of exciton processes

We assess the possibility to use an ambipolar organic light-emitting transistor structure as gain medium for an electrically pumped laser. Singlet and triplet continuity equations are solved together with Poissons and drift-diffusion equations in two dimensions. The solution allows for a detailed balance between the exciton decay, quenching and generation mechanisms. Simulations of a tetracene light-emitting transistor show that triplets are most dominant in quenching singlets. Singlet–triplet quenching can ultimately prevent pure tetracene crystals or films—when provided with a realistic optical feedback structure, to reach the threshold for stimulated emission.

Improving the Quality of Epitaxial Foils Produced Using a Porous Silicon-based Layer Transfer Process for High-Efficiency Thin-Film Crystalline Silicon Solar Cells

A porous silicon-based layer transfer process to produce thin (30-50 μm) kerfless epitaxial foils (epifoils) is a promising approach toward high-efficiency solar cells. For high efficiencies, the epifoil must have high minority carrier lifetimes. The epifoil quality depends on the properties of the porous layer since it is the template for epitaxy. It is shown that by reducing the thickness of this layer and/or its porosity in the near-surface region, the near-surface void size is reduced to <;65 nm and in certain cases achieve a 100 nm-thick void-free zone below the surface. Together with better void alignment, this allows for a smoother growth surface with a roughness of <;35 Å and reduced stress in the porous silicon. These improvements translate into significantly diminished epifoil crystal defect densities as low as ~420 defects/cm 2. Although epifoils on very thin porous silicon were not detachable, a significant improvement in the lifetime (diffusion length) of safely detachable n-type epifoils from ~85 (~300 μm) to ~195 μs (~470 μm) at the injection level of 10 15/cm 3 is achieved by tuning the porous silicon template. Lifetimes exceeding ~350 μs have been achieved in the reference lithography-based epifoils, showing the potential for improvement in porous silicon-based epifoils.

Influence of the contact metal on the performance of n-type carbonyl-functionalized quaterthiophene organic thin-film transistors

Organic thin-film transistors using 5, 5‴-diperfluorohexylcarbonyl-2,2′:5′,2″:5″,2‴-quaterthiophene (DFHCO-4T) as the electron conducting organic semiconductor are fabricated and the performance of these transistors with different top-contact metals is investigated. Transistors with Au source-drain top contacts attain an apparent saturation mobility of 4.6 cm2/V s, whereas this parameter is 100 times lower for similar transistors with Al/LiF top contacts. We explain this lower performance by the formation of a thin interfacial layer with poor charge injection properties resulting from a redox reaction between Al and DFHCO-4T.

A compact model for polycrystalline pentacene thin-film transistor

A compact physical model for the operation of polycrystalline pentacene thin-film transistors is presented here, valid in both linear and saturation regimes by including the Gaussian energy distribution of the grain-boundary traps. The effect of the temperature is also taken into account. The proposed model has been verified by comparing the simulated results with the experimental data.

An organic charge trapping memory transistor with bottom source and drain contacts

We present an organic charge trapping memory transistor with lithographically defined bottom source and drain contacts. This device can be written and erased at voltages as low as 15 V. More than 500 write and erase cycles and the retention of the trapped charge over more than three months are shown, demonstrating the possibilities of this device as a reprogramable nonvolatile organic memory element.

18% Efficiency IBC Cell With Rear-Surface Processed on Quartz

In order to relax the mechanical constraints of processing thin crystalline Si wafers into highly efficient solar cells, we propose a process sequence, where a significant part of the process is done on module level. The device structure is an interdigitated-back-contact cell with an amorphous silicon back surface field. The record cell reaches an independently confirmed efficiency of 18.4%. Although the device deserves further optimization, the result shows the compatibility of processing on glass with efficiencies exceeding 18%, which opens the door to a high-efficiency solar cell process where the potentially thin wafer is attached to a foreign carrier during the full processing sequence.

High-quality epitaxial foils, obtained by a layer transfer process, for integration in back-contacted solar cells processed on glass

Foil creation by lifting off a thin layer of a high quality silicon substrate is one of the promising substitutes for wafer sawing to create substrates thinner than 100 μm. The porous silicon-based layer transfer process is a well known method to obtain high quality foils. Despite a number of convincing lab-based solar cell show-cases, there is no breakthrough of this technology at (semi)-industrial level, because of the poor yield of processing free standing foils. This paper presents a method to fabricate back contacted solar cells based on epitaxial foils avoiding processes on free-standing foils. First, a porous silicon layer is electrochemically etched, acting as a weak sacrificial layer to detach the foil that is epitaxially grown on top of the porous silicon layer. Characterization of the epitaxial foils shows a good crystalline quality and an effective lifetime around 100 μs. Those results give indications that the obtained foils are well suited for solar cell fabrication. Front-side processing is done while the epitaxial foil is still attached to its parent substrate. A good yield is obtained for epitaxial foils that underwent the front-side processing sequence consisting of wet chemical texturing, FSF formation, passivation and ARC deposition. Afterwards, the front-side of the foil is bonded to a glass carrier and the foil is detached from its parent substrate. Silicone adhesives are used for this permanent bond. The rear-side of the solar cell is processed while bonded to glass. Therefore, only low temperature processes (<;200°C) can be used. So far, the rear-side processing sequence was performed on Float-zone reference wafers as a proof of concept resulting in a confirmed maximum efficiency of 18.4%. The rear-side processing sequence still needs to be applied on epitaxial foils.

Crystallisation dynamics in wide-bandgap perovskite films

Organic–inorganic metal halide perovskite materials have evolved as highly efficient photovoltaic materials with a controllable range of bandgaps. This trait offers exciting prospects for the application of perovskites as wide-bandgap thin-film top solar cells in tandem architectures with crystalline silicon bottom solar cells. In this work, we present a systematic material study on spin-coated methylammonium lead trihalide (CH3NH3Pb(I0.6Br0.4)3) that has a band gap of 1.77 eV, optimal for tandem architectures with crystalline silicon. Using a combination of X-ray diffraction, time-resolved photoluminescence, and scanning electron microscopy techniques, we determine the strong impact of annealing temperature and duration on perovskite film crystallinity, carrier lifetime, and average grain size. We further demonstrate a clear correlation between solar cell performance and crystallisation dynamics in the perovskite films. With optimised crystallisation of the perovskite films, our solar cells exhibit peak power conversion efficiency of 10.6% that stabilises at 9.0% after 10 minutes of maximum power point tracking. Finally, the activation energy for grain boundary mobility, and grain growth exponents are determined via quantitative analysis of grain growth kinetics, and hence, perovskite film quality.