Haris Osman

Above-IC generic poly-SiGe thin film wafer level packaging and MEM device technology: Application to accelerometers

We present an attractive poly-SiGe thin film packaging and MEM (Micro Electro-Mechanical) platform technology for integrating various packaged MEM devices above standard CMOS. The packages, having cavities as large as 1mm2, make use of pillars designed to withstand subsequent molding during 1st level packaging. Covers on top of the release holes avoid deposition inside the cavity during sealing. Hermeticity is proven in vacuum, air and N2 atmosphere and at different temperatures. Packaged functional accelerometers sealed at a pressure around 1bar, have an equivalent performance in measuring accelerations of about 1g compared to a piezoelectric commercial reference device.

Poly-SiGe-Based MEMS Thin-Film Encapsulation

This paper presents an attractive poly-SiGe thin-film packaging and MEM (microelectromechanical) platform technology for the generic integration of various packaged MEM devices above standard CMOS. Hermetic packages with sizes up to 1 mm2 and different sealed-in pressures ( ~ 100 kPa and ~ 2 kPa) are demonstrated. The use of a porous cover on top of the release holes avoids deposition inside the cavity during sealing, but leads to a sealed-in pressure of approximately 100 kPa, i.e. atmospheric pressure. Vacuum ( ~ 2 kPa) sealing has been achieved by direct deposition of a sealing material on the SiGe capping layer. Packaged functional accelerometers sealed at around 100 kPa have an equivalent performance in measuring accelerations of about 1 g compared to a piezoelectric commercial reference device. Vacuum-sealed beam resonators survive a 1000 h 85°C/85%RH highly accelerated storage test and 1000 thermal cycles between -40°C and 150°C.

SiGe MEMS technology: a platform technology enabling different demonstrators

In imecs 200mm fab a dedicated poly-SiGe above-IC MEMS (Micro Electro-Mechanical Systems) platform has been set up to integrate MEMS and its readout and driving electronics on one chip. In the Flemish project Gemini the possibilities of this platform have been further explored together with the project partners. Three different demonstrators were realized: mirrors for display applications, grating light valves (GLV) and accelerometers. Whereas the mirrors and GLVs are made with a similar to 300 nm thick SiGe structural layer plus optical coating, the SiGe structural layer thickness for the accelerometers is 4 mu m in order to improve the capacitive readout of in-plane devices. The processing and measurement results of these functional demonstrators are shown in this paper. These new demonstrators reconfirm the generic nature of the SiGe MEMS platform.

Submicron three-terminal SiGe-based electromechanical ohmic relay

This paper demonstrates functional NEM cantilever relays fabricated in a CMOS-compatible low-T (400°C) CVD SiGe process flow. Devices with a length in the micrometer range (<;3μm), a width in the range 0.2-1μm, a thickness and a gap of below 100nm were successfully fabricated and characterized. A high on/off current ratio (of better than 10⁸:1), a subthreshold swing (S) better than 150μV/decade and “essentially zero” off-state leakage current were experimentally observed. A life time of minimum 10³ switching cycles was demonstrated. A maximum current density of around 10μA/μm² without causing stiction due to Joule-heating was found.

Wafer bow of substrate transfer process for GaNLED on Si 8 inch

This paper investigates the wafer bow induced during the substrate transfer process for GaN LED on Si (111) 8 inch wafers. The substrate transfer process is to transfer the thin GaN LED device layer to a carrier wafer using a CuSnCu permanent bonding layer. The process generates tensile bow on a wafer due to the high tensile stress of the Cu or the CuxSny intermetallic layer after bonding. Understanding the wafer bow evolution during the substrate transfer is very important to get a good control of the process. The high wafer bow value may cause problems for some automatic handling tools in the production line or affect process quality such as in lithography. The influence of substrate thickness and Cu metallization thickness on the wafer bow has been studied. A bow compensation layer can be used to compensate the tensile bow, thus minimizing the wafer bow after the substrate transfer process.

Detection, binning, and analysis of defects in a GaN-on-Si process for High Brightness Light Emitting Diode's

High Brightness Light Emitting Diodes (HB-LEDs) have received considerable attention during the last few years due to their utilization in numerous consumer products (automotive, displays, etc.). Recently, one of the largest emerging markets for HB-LEDs is the lighting industry because of its lower power requirements and longer lifetime. One of the key limitations for its universal consumer adoption is its higher cost. If the cost for production of an HB-LED is broken up into materials and process steps the price of the sapphire substrate is noticed to be significantly higher than all the individual process and material steps. In such a circumstance the key to making HB-LEDs cheaper is by substrate engineering. Another aspect of the cost is the fact that the traditional sapphire substrates are usually 2 or 4 inches. Therefore, a logical step forward is to move to bigger substrates where yield can be higher. To make this a reality different groups have been working on alternative cheaper and larger substrates (Si/Glass). However, before any technology becomes mature numerous reliability and yield issues need to be fixed. As part of process optimization identifying killer defects is critical. In order to do so we use the Candela platform from KLA Tencor to monitor our epitaxial process. Since, silicon wafers are one of the most common substrates available it obviously emerged as a first choice. We at IMEC have developed a GaN on Si process for making HB-LEDs on 200mm Si (111) substrates. The control of the first epitaxial layers on Si is the key to a successful HB-LED fabrication. Lattice mismatch and thermal coefficient mismatch often lead to wafer bow and defect propagation to the p-GaN surface which can be detrimental to the IQE (Internal Quantum Efficiency). The goal of this work is to understand the different types of defect and the nature of their origin on a typical HB LED stack as well as the detection capability of the tool. Typical defects detected are the cracks/hexagonal defects/pits and particles. Defect data will be analyzed in terms of compressive or tensile stress in the film. This paper focuses on un-optimized EPI wafers in terms of stress/defectivity and crystalline quality to help define the correct inspection thresholds.

Contact reliability improvement of a poly-SiGe based nano-relay with titanium nitride coating

This work reports a TiN coated contact implemented in a vertically actuated SiGe-based Nano-Electro-Mechanical (NEM) relay. It is shown that covering the bottom of the movable SiGe beam (the armature) with a TiN layer in the contact region will improve the contact performance of the relay with lowering the on-resistance, RON, by around 4 orders of magnitude and by enhancing the number of switching cycles without degradation. This NEM relay provides an optimal combination of small motional volume (~0.02μm3) and long mechanical lifetime (> 1010 in vacuum). Furthermore, with a total contact area of 0.01μm2 (among the smallest reported so far), an on-resistance of ~1MΩ has been achieved.

Quantum efficiency and dark current evaluation of a backside illuminated CMOS image sensor

We report on the development and characterization of monolithic backside illuminated (BSI) imagers at imec. Different surface passivation, anti-reflective coatings (ARCs), and anneal conditions were implemented and their effect on dark current (DC) and quantum efficiency (QE) are analyzed. Two different single layer ARC materials were developed for visible light and near UV applications, respectively. QE above 75% over the entire visible spectrum range from 400 to 700 nm is measured. In the spectral range from 260 to 400 nm wavelength, QE values above 50% over the entire range are achieved. A new technique, high pressure hydrogen anneal at 20 atm, was applied on photodiodes and improvement in DC of 30% for the BSI imager with HfO2 as ARC as well as for the front side imager was observed. The entire BSI process was developed 200 mm wafers and evaluated on test diode structures. The knowhow is then transferred to real imager sensors arrays.

Substrate transfer for GaN-based LEDs on 200mm Si

This paper presents a substrate transfer process for GaN-based LEDs on 200mm Si wafer. The LED active layers are first grown on a 200mm-Si (111) substrate using the MOCVD method and LED devices are fabricated. Then a post-process is applied after the fabrication of LED devices to transfer the GaN-LED to a Si substrate carrier using permanent metallic bonding. In this process, the GaN-LED wafer is bonded to a carrier and Si substrate on the device wafer is totally removed to improve the light extraction efficiency of LED devices. Process step development for the important steps such as bonding, thinning, GaN surface texturing are described. The use of large size 200mm Si wafer and standard IC facility promises low cost and high volume production of LED devices.

Gan-on-Si process defect detection and analysis for HB-LEDs and power devices

The race to gallium-on-silicon (GaN-on-Si) has been a heated one simply because growth of defect-free GaN-on Si is not an easy problem. The main impetus for this stack comes from a combination of factors, including the ability to use large and cheaper substrates and access to automated back-end manufacturing tools in depreciated IC fabs. Study of the different types of defects during GaN epitaxy is the main goal of this paper. In order to do so, we use scatterrometry is used to analyze different signals. Setting the correct thresholds between signal and noise is key in detecting the defects of interest.