Deniz Sabuncuoglu Tezcan

3D integration by Cu-Cu thermo-compression bonding of extremely thinned bulk-Si die containing 10 μm pitch through-Si vias

Using standard single damascene type techniques on bulk-Si, combined on one hand with extreme wafer thinning and on the other with Cu-Cu thermo-compression bonding technology, the paper demonstrate yielding 10k through-wafer 3D-via chains with a via pitch of 10μm for a via diameter of 5μm. The bonded contacts exhibit shear strengths exceeding 40MPa. Measurements indicate there is no significant contact resistance at the Cu-Cu bonded interface: within measurement accuracy, the 4-point via chain resistance is consistent with bulk Cu resistivity

Through-silicon via and die stacking technologies for microsystems-integration

The highest integration density of microsystems can be obtained using a 3D-stacking approach, where each layer of the stack is realized using a different technology, which may include sensors, imagers, rf and MEMS technologies. A key challenge is however to perform such stacking in a cost-effective manner. In this paper, a novel 3D TSV and 3D stacking technologies will be presented. Application examples are MEMS packaging and heterogeneous integration of imaging devices.

Sloped Through Wafer Vias for 3D Wafer Level Packaging

Through silicon via (TSV) technology is one of the critical and enabling technologies for 3D chip stacking. Many TSV approaches that have been demonstrated are application specific; and there is a great need for generic solutions. This work describes the design, fabrication and characterization of a TSV technology for silicon substrates where the interconnects are fabricated typically after standard CMOS processing and can be applied to any silicon based technology. This so-called 3D Wafer Level Packaging (3D-WLP) technology die stacking is based on a the thinning first, via last approach: the via is fabricated from the backside of a thinned wafer. Plasma etching of the wafer is used to achieve sloped profde which allows the conformal deposition of the dielectric layer and copper seed metallization. The vias are isolated from the substrate using polymer dielectrics; and spray coating of photoresist is used to pattern the dielectric within the vias. Electrical connection between the front and the back of the wafer is achieved by partial filling of the vias with copper. All processes employed in the fabrication of sloped through wafer vias are performed using standard wafer handling and at low temperature (< 250degC) for post CMOS compatibility. Various dimensions of TSVs are fabricated and electrically characterized by four point measurements. The measurements and calculations on daisy chains connecting a number vias in series show that the via resistance is in the range of 20-30mOmega depending on the via size. We believe that this generic 3D-WLP via approach is suitable for many 3D applications.

Scalable Through Silicon Via with polymer deep trench isolation for 3D wafer level packaging

A scalable generic Through Silicon Via (TSV) process is developed using spin-on dielectric polymer as isolation layer where deep annular trenches in Silicon are filled with the polymer. Following parameters are found to be affecting the polymer material spreading on the wafer surface and the filling performance: pre-treatments on the wafer surface, TSV density and physical properties of the polymer. Yielding TSV chains are measured on the fabricated wafers and the TSV resistance is found to be ≪100mΩ. It is a via-last TSV process which is applicable to any silicon technology.

3-D Wafer-Level Packaging Die Stacking Using Spin-on-Dielectric Polymer Liner Through-Silicon Vias

In this paper, we report on the processing and the electrical characterization of a 3-D-wafer level packaging through-silicon-via (TSV) flow, using a polymer-isolated, Cu-filled TSV, realized on thinned wafers bonded to temporary carriers. A Cu/Sn micro-bump structure is integrated in the TSV process flow and used for realizing a two-die stack. Before TSV processing, the Si wafers are bonded to temporary carriers and thinned down to 50 μm. The actual TSV and micro-bump process uses 3 masks, two Si-deep-reactive ion etching steps and a polymer liner as a dielectric. The dimensions of the TSV structure are: 35 μm ØTSV, 5 μm thick polymer liner, 25-μm-Ø Cu TSV, 50 μm deep TSV, and a 60 μm TSV pitch.

Development of vertical and tapered via etch for 3D through wafer interconnect technology

Two types of dry silicon etch techniques are developed to cover two different areas of demand for interconnect technology: one for high aspect ratio (AR) vertical vias and one for tapered vias. Various sizes of vertical vias and trenches with diameters/widths ranging from 1-100 mum with an AR up to 50 are realized using Bosch deep reactive ion etch (DRIE) process. A linear model is applied to describe and to give physical insight in the aspect ratio dependant etch (ARDE) effect. The feasibility of the vertical vias as electrical interconnect is shown by isolating them from the substrate by silicon oxide and then filling with polysilicon. The tapered vias are typically post-processed on fabricated device wafers, making it inherently a more generic approach where diameter size can be large and low AR can be tolerated. Vias with a depth of ~100 mum and a diameter of ~50mum at the bottom (though larger at top) are realized. Varying various etch parameters, slope angles of 70deg-80deg are realized to allow for conformal deposition of dielectric/seed materials on the sidewalls and to allow lithography within the via. Reactive ion etch (RIE) is used to fabricate sloped vias by simultaneously applying etch and passivation gasses. Negative angles on the via top and sidewall roughness are observed that introduce conformal coating problems and increased leakage currents. Smoothening techniques using maskless wet and dry silicon etching are investigated to overcome these problems.

High performance Hybrid and Monolithic Backside Thinned CMOS Imagers realized using a new integration process

Hybrid and monolithic thinned backside illuminated CMOS imagers operating at full depletion at low substrate voltages were developed. The combination of a 50 mum EPI layer with varying doping concentration and trenches to reduce crosstalk is unique. All thin wafer processing is performed on 200 mm wafers using a specially developed temporary carrier process. As a result, working imagers exhibiting high pixel yield, high quantum efficiency and low dark current are demonstrated

Photoresist coating and patterning for through-silicon via technology

Three-dimensional (3D) integration requires through-wafer interconnects, i.e. an integration of electrical connections from one side of the wafer to the other side. In some cases, it involves the lithographic patterning of through-Si via (TSV). For this step, a conformal coating of a resist layer is necessary. In this paper, we present two potential photoresist coating methods for coating a wafer with TSV: spray coating and electrodeposition (ED) of the photoresist. Lithographic patterning inside the TSV is also investigated. Some parameters that influence the pattern definition, such as large gap exposure, resist thickness and via size, are identified and evaluated.

Impact of the limitations of state-of-the-art micro-fabrication processes on the performance of pillar array columns for liquid chromatography

We report on the practical limitations of the current state-of-the-art in micro-fabrication technology to produce the small pillar sizes that are needed to obtain high efficiency pillar array columns. For this purpose, nine channels with a different pillar diameter, ranging from 5 to 0.5 μm were fabricated using state-of the-art deep-UV lithography and deep reactive ion etching (DRIE) etching technology. The obtained results strongly deviated from the theoretically expected trend, wherein the minimal plate height (H(min)) would reduce linearly with the pillar diameter. The minimal plate height decreases from 1.7 to 1.2 μm when going from 4.80 to 3.81 μm diameter pillars, but as the dimensions are further reduced, the minimal plate heights rise again to values around 2 μm. The smallest pillar diameter even produced the worst minimal plate height (4 μm). An in-depth scanning electron microscopy (SEM) inspection of the different channels clearly reveals that these findings can be attributed to the micro-fabrication limitations that are inevitably encountered when exploring the limits of deep-UV lithography and DRIE etching processes. When the target dimensions of the design approach the etching resolution limits, the band broadening increases in a strongly non-linear way with the decreased pillar dimensions. This highly non-linear relationship can be understood from first principles: when the machining error is of the order of 100-200 nm and when the target design size for the inter-pillar distance is of the order of 250 nm, this inevitably leads to pores that will range in size between 50 and 450 nm that we want to highlight with our paper highly non-linear relationship. This highly non-linear relationship can be understood from first principles: when the machining error is of the order of 100-200 nm and when the target design size for the inter-pillar distance is of the order of 250 nm, this inevitably leads to pores that will range in size between 50 and 450 nm.

Parylene N as a dielectric material for through silicon vias

This paper reports on the feasibility of parylene N as a dielectric material for through silicon vias (TSV). TSV are the key enabling technology for 3D wafer laver packaging. Parylene is used as an insulating material in one of the approaches adopted for realizing 3D wafer level packaging at IMEC. This paper discusses main issues regarding the processing of parylene N for the TSV application. First, the thickness uniformity of as-deposited parylene across the wafer and inside the via is investigated. The results show that for 200 mm wafers, within-wafer and wafer-to-wafer thickness is sufficiently uniform. The 1-sigma thickness variation of less than 4 percent for both cases is measured. 1 sigma thickness variation of less than 5 percent is observed from batch to batch. Second, the effect of substrate, temporary glue layer and carrier wafer for thinned device wafers on the dry etching of parylene is analyzed. The experiments show that the etching was sufficiently uniform across the wafer; and the uniformity across the surface is recorded to be greater than 95 percent. There is no considerable effect of substrate or bonding layer thickness, however carrier wafer influence the etching rate.