Harsh Naik
Rensselaer Polytechnic Institute
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Publication
Featured researches published by Harsh Naik.
Materials Science Forum | 2014
Harsh Naik; T. Paul Chow
This paper compares the performance of 4H-SiC MOS capacitors and MOSFETs made using the conventional NO annealing process and a high-temperature (1400°C) dry oxidation process. Through extensive C-V, G-ω, I-V and Hall measurements, the limitations of both the processes are discussed.
Materials Science Forum | 2009
Harsh Naik; K. Tang; T. Marron; T.P. Chow; Jody Fronheiser
The effect of using different orientations of 4H-SiC substrates on the performance of 4H-SiC MOSFETs has been evaluated. Three sets of samples with (0001), (000-1) and (11-20) oriented SiC substrates were used to fabricate the MOSFETs, with a gate oxide process consisting of a low- temperature deposited oxide followed by NO anneal at 1175°C for 2hrs. Various device parameters, particularly threshold voltage, subthreshold slope, field-effect mobility, inversion sheet carrier concentration and Hall mobility have been extracted. Temperature characterization up to 225°C was also performed.
Materials Science Forum | 2012
Alex V. Bolotnikov; Peter Almern Losee; Kevin Matocha; Jeff Nasadoski; John Stanley Glaser; Stephen Daley Arthur; Zachary Stum; Jerome L. Garrett; Ahmed Elasser; Ljubisa Dragoljub Stevanovic; Harsh Naik; T. Paul Chow
This paper presents a study of performance and scalability of 8kV SiC PIN diodes focusing on area-dependent yield and sensitivity to material properties variation. Successfully fabricated 18 and 36 mm2 SiC-PiN diodes exhibited avalanche breakdown above 8 kV and < 5V forward voltage drop at 100 A/cm2 current density. The fast switching operation of these diodes up to ~5 kHz frequency is evidenced by reverse recovery measurements with by double-pulse inductive switching tests. The devices exhibit 0.142 and 0.169 uC/cm2 stored charge at room temperature and 125oC, respectively, when turned-off from Jf = 100A/cm2 to Vr = 2.1 kV. The measured diode breakdown voltage exhibited location and size dependent yield, indicating the necessity of material quality improvements for production.
International Journal of High Speed Electronics and Systems | 2011
Harsh Naik; Tom Marron; T. Paul Chow
We report for the first time operation of GaN Schottky rectifiers under cryogenic temperatures. A 600V, 4A GaN Schottky rectifiers from Velox Semiconductors has been used for the characterization. Forward conduction and reverse blocking performance was measured down to 77K. Two Schottky barrier heights have been noticed at low temperatures and a tunneling limited reverse leakage current was observed for the rectifier.
Materials Science Forum | 2011
Harsh Naik; T. Paul Chow
The effect of using two different polytypes, 4H-SiC and 6H-SiC, on the performance of (0001) SiC MOSFETs has been studied. 4H-SiC and 6H-SiC MOSFETs have been fabricated with deposited gate oxides followed by oxidation in dry O2 or NO. Device parameters, particularly field-effect mobility, inversion sheet carrier concentration and Hall mobility have been extracted. We have also compared the mobility-limiting mechanisms of (0001) 4H and 6H-SiC MOSFETs and found that inversion mobility can be further improved in 4H-SiC, but not 6H-SiC.
Materials Science Forum | 2010
Harsh Naik; Zhongda Li; T. Paul Chow
High temperature C-V characterization with and without UV illumination has been performed on n-type 4H-SiC MOS capacitors fabricated using different processing conditions to extract various types of interfacial charges. An anomalous positive flatband voltage shift with temperature has been observed in most of the SiC MOS capacitors measured. We have experimentally identified an extra type of fixed charges at the 4H-SiC/SiO2 interface from the temperature dependence of the flatband voltage, particularly under UV illumination.
Materials Science Forum | 2014
Zachary Stum; Yi Tang; Harsh Naik; T. Paul Chow
A new power law is approximated for effective impact ionization in 4H-SiC, which is then used to generate one-dimensional equations for critical electric field, avalanche breakdown voltage, and depletion layer width that match both simulation and published device results better than previous published equations.
Materials Science Forum | 2012
Harsh Naik; Zhongda Li; H. Issa; Y.L. Tian; T. Paul Chow
The strong covalent bond of SiC imposes harsh post implantation annealing condition requirement for SiC MOS devices. As a consequence the effect of the annealing conditions on the channel region of the MOS devices becomes critical. High temperature microwave annealing has been shown to be an attractive alternative to conventional thermal annealing techniques. The effect of high temperature rapid microwave annealing on the performance of 4H-SiC MOS capacitors has been studied in this paper. Annealing temperatures ranging from 1600°C up to 2000°C for 30secs is used and the effect of annealing conditions is studied via C-V measurements on MOS capacitors.
2012 Lester Eastman Conference on High Performance Devices (LEC) | 2012
Zhongda Li; Harsh Naik; T. Paul Chow
Physica Status Solidi (c) | 2011
Harsh Naik; Tom Marron; T. Paul Chow