Zhongda Li

Sidewall Dominated Characteristics on Fin-Gate AlGaN/GaN MOS-Channel-HEMTs

The fin-gate structure was fabricated onto AlGaN/GaN MOS channel-high electron mobility transistors (MOSC-HEMTs), and the fin sidewall contribution to the MOS channel characteristics was investigated. In fin-gate MOSC-HEMTs (Fin-MOSC-HEMTs) with 120-nm fin width, significant suppression of short channel effect is obtained, but the threshold voltage (Vth) becomes lower than that of conventional MOSC-HEMTs. The fin width dependence shows continuous Vth decrease by decreasing the fin width, indicating that the narrower fin-gate channel is dominated by the fin sidewalls that are depletion mode nature. The channel sheet resistance extracted from channel length dependence and device transconductance for Fin-MOSC-HEMTs are superior to those of conventional MOSC-HEMTs when they are normalized by effective gate width as the summation of fin width, indicating contribution from sidewalls to channel conduction. Temperature dependence of Vth shows clearly different behavior between the MOSC-HEMT and Fin-MOSC-HEMT. These results demonstrate sidewall-dominated characteristics of these Fin-MOSC-HEMTs.

Design and Simulation of 5–20-kV GaN Enhancement-Mode Vertical Superjunction HEMT

The systematic design process using numerical simulations of the novel gallium nitride (GaN) enhancement-mode vertical superjunction high electron mobility transistor (HEMT) with breakdown voltage (BV) in the range of 5-20 kV is presented. The GaN superjunction pillar structure in the drift region of the vertical HEMT is first optimized using a simpler GaN superjunction diode structure, and the optimum half-pillar charge dosage is obtained to be 8×1012 cm-2, which is consistent with the value estimated from the Gausss Law. The GaN vertical superjunction HEMT is then simulated and optimized, and the Ron,sp-BV tradeoff curves in the range of 5-20 kV are obtained by varying the epi thickness. The Ron,sp-BV tradeoff is found to improve with smaller pillar width as in silicon superjunction MOSFETs, and the best Ron,sp of 4.2 mΩ-cm2 with BV of 12.4 kV is projected with half-pillar width of 3 μm. The robustness of the superjunction HEMT is also examined using structure with half-pillar width of 8 μm, and compared with the GaN vertical HEMT with conventional drift layer and same dimensions. The simulated on-state BV of the GaN vertical superjunction HEMT shows a 4.5% drop from the off-state BV and is only slightly higher than the 1.7% drop of the conventional GaN vertical HEMT.

Metal?Oxide?Semiconductor Interface and Dielectric Properties of Atomic Layer Deposited SiO2 on GaN

The dielectric and MOS interface properties of SiO2 deposited with atomic layer deposition (ALD) on GaN with different surface treatments have been investigated with DC current–voltage (I–V) measurements and UV-assisted capacitance–voltage (C–V) measurements. Dielectric breakdown characteristics and leakage conduction mechanism for ALD SiO2 depend on surface conditions. Dry etch with NaOH post-etch GaN surface exhibited high oxide breakdown voltage with small distribution, larger barrier height characteristics, and higher charge to breakdown characteristics when compared with un-etched surface condition and dry etch with tetramethylammonium hydroxide (TMAH) post-etch surface condition. Moreover, fixed charge density and interface trap density at MOS interface extracted by UV-assisted C–V were comparable between un-etched surface sample and dry etch with NaOH post-etch surface sample, indicating dry etching damage recovery and demonstrating the usability of NaOH post-etching treatment. Comparison has also been made to a composite oxide of SiO2/Al2O3/SiO2, showing possibility of oxide charge engineering toward positive threshold voltage but carrier trapping by insertion of Al2O3.

Experimental Identification of Extra Type of Charges at SiO2/SiC Interface in 4H-SiC

High temperature C-V characterization with and without UV illumination has been performed on n-type 4H-SiC MOS capacitors fabricated using different processing conditions to extract various types of interfacial charges. An anomalous positive flatband voltage shift with temperature has been observed in most of the SiC MOS capacitors measured. We have experimentally identified an extra type of fixed charges at the 4H-SiC/SiO2 interface from the temperature dependence of the flatband voltage, particularly under UV illumination.

Study of High Temperature Microwave Annealing on the Performance of 4H-SiC MOS Capacitors

The strong covalent bond of SiC imposes harsh post implantation annealing condition requirement for SiC MOS devices. As a consequence the effect of the annealing conditions on the channel region of the MOS devices becomes critical. High temperature microwave annealing has been shown to be an attractive alternative to conventional thermal annealing techniques. The effect of high temperature rapid microwave annealing on the performance of 4H-SiC MOS capacitors has been studied in this paper. Annealing temperatures ranging from 1600°C up to 2000°C for 30secs is used and the effect of annealing conditions is studied via C-V measurements on MOS capacitors.