Harsupreet Kaur

Two-dimensional subthreshold analysis of sub-micron GaN MESFET

An analytical two-dimensional (2D) model to accurately predict the channel potential and electric field distribution in sub-micron GaN MESFET operating in the sub-threshold regime based on (2D) analytical solution of Poissons equation using superposition principle is presented. The results so obtained for channel potential, electric field, threshold voltage, etc are compared with simulated data using ATLAS 2D device simulator. The model is then extended to predict the current voltage characteristics and the effects of drain induced barrier lowering (DIBL) on the performance. Furthermore, the sub-threshold output characteristics of the device are also interpreted qualitatively.

A semi empirical approach for submicron GaN MESFET using an accurate velocity field relationship for high power applications

Abstract A semi empirical model has been proposed for sub-micron GaN MESFETs to calculate the I–V characteristics using an accurate velocity-field relationship obtained by fitting it with the Monte Carlo (MC) simulation. The results so obtained are compared with the experimental results to validate our model and are also compared with the results obtained from the simple saturation model to present the influence of electron drift velocity modeling on the device parameters. The model has been extended to predict the microwave parameters such as transconductance and output conductance of the device.

Modeling and analysis of Double Gate Ferroelectric Junctionless (DGFJL) transistor

In this paper we have developed an analytical model for Double Gate Ferroelectric Junctionless (DGFJL) transistor using Landaus theory and parabolic potential approximation. We have obtained expressions for surface potential and electric field and have demonstrated negative capacitance effect provided by ferroelectric layer. The results also demonstrate the step-up conversion capability of this device, thereby signifying improved gate control and the suitability of this device for low voltage/low power switching applications.

Asymmetric Gate Stack Surrounding gate Transistor (ASYMGAS SGT): 2-D Analytical Threshold Voltage Model

In the present work, a two-dimensional analytical model for novel device architecture, asymmetric gate stack surrounding gate transistor (ASYMGAS SGT) is presented and its effectiveness in suppressing short channel effects and hot carrier effects is investigated. The model is developed by solving the Poisson equation in cylindrical coordinates assuming a parabolic potential profile in the radial direction. Using the model, the expressions for potential and electric field have been obtained and the analysis is extended to obtain the threshold voltage of the device. It is demonstrated that besides improving the short channel immunity and hot carrier reliability, incorporation of asymmetric gate stack architecture also leads to enhanced transport efficiency. In order to verify the model, the analytical results have been compared with the simulated data obtained from device simulator ATLAS and a good agreement is found.

Impact of laterally asymmetric channel and gate stack design on device performance of surrounding gate MOSFETs : A modeling and simulation study

A two-dimensional analytical model is presented to study the impact of LACGAS device on the device characteristics. It is demonstrated that LACGAS leads to suppression of short channel effects such as threshold voltage (Vth) roll-off, drain induced barrier lowering (DIBL) and hot carrier effects. It also improves the transport efficiency owing to a greater gate control which is achieved by incorporating the stack architecture. Furthermore, LACGAS design also enables to obtain a high current drivability and enhancement in transconductance.

Analytical drain current model to study the impact of negative capacitance phenomenon in Symmetric Double Gate Junctionless Transistor

We have developed a complete drain current model to study the impact of negative capacitance phenomenon exhibited by ferroelectric materials in Symmetric Double Gate Junctionless Transistor using Pao-Sah current formulation and Landau Devonshire theory. Strontium Bismuth Tantalate (SBT) is used as gate insulator and no interface layer is considered in the analysis i.e. metal-ferroelectric-semiconductor (MFS) structure has been studied. Using the analytical model the various parameters obtained are gain, gate capacitance, subthreshold swing, threshold voltage, mobile charge density and drain current. It has been observed that values of gain>1 and subthreshold swing<60mV/dec can be achieved, thereby, signifying that device has suitability for faster, energy efficient switching applications.

Analytical model to study temperature dependent Negative Capacitance effect on long channel Double Gate Ferroelectric Junctionless Transistor

In this work, we have theoretically investigated the impact of temperature dependent Negative Capacitance (NC) effect on electrical characteristics of long channel Double Gate Ferroelectric Junctionless Transistor for temperature range 280 to 340K. We have considered metal-ferroelectric-semiconductor (MFS) structure and incorporated ferroelectric material Strontium Bismuth Tantalate (SBT) as gate insulator. The impact of temperature variation on electrical parameters such as surface potential, gain, gate capacitance, and mobile charge density has been studied. It has been observed that internal voltage amplification decreases with increase in temperature. Also, degradation of gain and gate capacitance is observed with gradual increase in temperature.

Asymmetric Multilayered Gate Dielectric (AMGAD) surrounding gate MOSFET: A new structural concept for enhanced device performance

A two-dimensional analytical model for asymmetric multilayered gate dielectric surrounding gate MOSFET (AMGAD SGT) is presented and its effectiveness in suppressing short channel effects and hot carrier effects is examined. The expressions for potential and electric field have been obtained and the analysis is extended to obtain the threshold voltage and subthreshold slope of the device. It has been established that incorporation of asymmetric multilayered gate dielectric design leads to enhanced carrier transport efficiency besides also improving the short channel immunity and hot carrier reliability. The model is verified by comparing the analytical results with the simulated data obtained from device simulator ATLAS and a good agreement is found.

An analytical model for admittance parameters of GaN MESFET for microwave circuit applications

An analytical model of GaN MESFET to evaluate admittance parameters is presented. Frequency dependence of the parasitic capacitances obtained by simulations has been utilized to develop the model. Results have been verified using ATLAS 2D device simulator.

Impact of laterally asymmetric channel and gate stack architecture on device performance of surrounding gate MOSFET (LACGAS SGT): A simulation study

In the present work, LACGAS SGT that integrates the advantages of both the LAC and stack architecture is proposed and its impact on device characteristics is studied using numerical simulations. Using numerical simulations, the novel features of LACGAS SGT have been studied and compared with CON and LAC devices and it has been shown that LACGAS design leads to enhanced device performance in comparison to CON and LAC devices.