Haruhiko Tanaka

A high-packing density pixel with punchthrough read-out method for an HDTV interline CCD

A new pixel structure for a high-packing-density interline CCD is proposed, in which signal charges are read out from the photodiodes to the vertical CCD by a punchthrough mechanism. This read-out method makes it possible to reduce the depth of the VCCD channel and the second p-well by implanting these two layers after diffusion of the photodiode n layer. Spreading resistance measurements on dummy wafers show that the depths of these layers are 0.28 /spl mu/m and 0.6 /spl mu/m, respectively. Moreover, the photodiode n-layer is covered with a surface p/sup +/-layer, even at the transfer region. We describe the results of simulations and experiments on a test image sensor with pixel dimensions of 7.3 /spl mu/m (H)/spl times/7.6 /spl mu/m (V). From the experimental data, we estimate the characteristics of an image sensor with pixel dimension 5.0 /spl mu/m (H)/spl times/5.2 /spl mu/m (V). Such a device should have a maximum charge handling capability of 1.4/spl times/10/sup 5/ electrons, a smear level of -88 dB, a sensitivity of 1.5/spl times/10/sup 3/ electrons/Ix with a 30% fill factor, no image lag, and a low photodiode dark signal of less than 14 electrons at 60/spl deg/C. These results indicate that an IL-CCD with a punchthrough readout structure is suitable for image sensors with a high pixel density such as 2/3 inch 2 million pixel image sensors for high-definition TV applications. >

A Proposal of a Highly Sensitive Interline CCD for HDTV

A solid-state imaging device for high-definition TV systems needs to have 5.tp 8 times as many pixels as conventional devices.l)2) This requir6nient, in conjunction with the need for miniaturization, makes it neces-sary_ t_o rgggce the pixel size. However, in an interline CCD,tp) which-is widely available on the market, the area of the vertical CC-D cannot be scaled down without sacrificing c.harge handling capability, ?Dd enlarging the signal band increases rand6m iroise bi the output amplifier.

Solid State Imaging Techniques. A Proposal for a 1/2-inch 2M-pixel Progressive Scan Line-amplified Multiple Multielectrode-potential-wells Charge-transfer Device.

Multiple multielectrode-potential-wells in the vertical CCD (VCCD) are formed by a shiftresistor and transfer charges at a high speed in horizontal blanking time. Signals are amplified, sample -holed at each VCCD output, and read out by a shiftresistor. The single-layer CCD/CMOS process and the VCCD driving circuitry, which generates transfer and readout pulse, realize these concepts. The 1/2-inch 2 M-pixel progressive scan image sensor is designed using 0.8-μm technology and its fundamental characteristics are evaluated. The sensor has a saturation signal charge of 3.4 × 104 electrons, a smear level of 92 dB, a sensitivity of 5.4 × 102 electrons/lx with a 40% fill factor, no picture degradation caused by pulsing a power dissipation of 89 mW, a random noise of 18 electrons, fixed pattern noises of 17 electrons in the dark and 2.5% in the light, and a chip size of 10.3 (H) × 6.0 (V) mm2.

Analysis of Smear Noise in Interline-CCD Image Sensor with Gate-Free Isolation Structure

A gate-free isolation structure for smear noise suppression was proposed for an Il(lnterline transfer) CCD image sensor. It was found from analyzing the smear components that the signal-to-smear ratio in the proposed structure is 30 dB larger than that in the conventional structure, and is comparable to that of FIT (Frame Interline lransfer) CCDs. These results are promising for making homeuse video cameras with high-definition IL-CCD image sensors. B-2-6