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Featured researches published by Dai Hisamoto.


reliability physics symposium | 1988

A new soft-error phenomenon in VLSIs: the alpha-particle-induced source/drain penetration (ALPEN) effect

Eiji Takeda; Dai Hisamoto; Tohru Toyabe

The alpha-particle source/drain penetration (ALPEN) effect is investigated using a 3-D device simulator (CADDETH) and a novel experimental method. A study of soft error due to alpha-particle injection has so far focused on such memory structures and circuits as DRAMs/SRAMs. However, a new soft error is expected to occur in single MOSFETs as the effective channel length becomes comparable to the funneling length. The authors describe: (1) the funneling penetration current between source and drain; (2) a new soft error (0 to 1) caused by the ALPEN effect; (3) experimental verification of the ALPEN effect; and (4) the impact on VLSI scaling. The ALPEN effect puts various constraints, such as the latch-up, emitter-to-collector short in bipolars, and punchthrough in parasitic MOSFETs, on VLSI design. Thus, the ALPEN effect will be a crucial factor in the scaling limits of future ULSIs with dimensions below 0.5 mu m. >


Applied Physics Letters | 1995

Evidence for ballistic transport of two‐dimensional electron gas at liquid‐nitrogen temperatures in a silicon metal–oxide semiconductor field effect transistor with a neck in the middle

Kan Takeuchi; Dai Hisamoto; Hisaomi Yamashita

The transconductance of a silicon metal–oxide semiconductor field effect transistor with a neck in the middle was measured at liquid‐nitrogen temperatures. The narrowest part of the gate with p+ isolations is 0.24 μm wide and about 0.2 μm long. The transconductance shows a peaked structure near the threshold voltage. The calculated transconductance based on the ballistic transport model of two‐dimensional electron gas explains well the peaked structure.


Applied Physics Letters | 1995

Oscillations at liquid‐nitrogen temperatures in the transconductance of a silicon metal‐oxide‐semiconductor field‐effect transistor with a neck in the middle

Kan Takeuchi; Dai Hisamoto; Masaaki Aoki

The conductance of a silicon metal‐oxide‐semiconductor field‐effect transistor, the gate of which has a neck in the middle, was measured at liquid‐helium temperatures and liquid‐nitrogen temperatures. The channel width in the neck region configured by SiO2 isolation regions is below 50 nm. The transconductance at liquid‐nitrogen temperatures shows periodic oscillations that are accentuated by negative substrate bias. We explain the results based on the one‐dimensional subbands formed in the neck region.


Archive | 1991

Semiconductor device and semiconductor memory device

Dai Hisamoto; Toru Kaga; Shinichiro Kimura; Masahiro Moniwa; Haruhiko Tanaka; Atsushi Hiraiwa; Eiji Takeda


Archive | 1992

Method for manufacturing a semiconductor device and a semiconductor memory device

Dai Hisamoto; Toru Kaga; Shinichiro Kimura; Masahiro Moniwa; Haruhiko Tanaka; Atsushi Hiraiwa; Eiji Takeda


Archive | 1992

Capacitive memory having a PN junction writing and tunneling through an insulator of a charge holding electrode

Dai Hisamoto; Shoji Shukuri; Kazuhiko Sagara; Shinichiro Kimura; Shinichi Minami; Eiji Takeda


Archive | 2003

Vertical semiconductor device with tunnel insulator in current path controlled by gate electrode

Dai Hisamoto; Kozo Katayama


Archive | 1993

Method of manufacturing a semiconductor device having silicon islands

Dai Hisamoto; Toru Kaga; Shinichiro Kimura; Masahiro Moniwa; Haruhiko Tanaka; Atsushi Hiraiwa; Eiji Takeda


Archive | 2000

Semiconductor device having SOI-MOSFET

Dai Hisamoto; Yoshimi Sudou


Archive | 1996

Semiconductor memory device and method of manufacturing same

Toru Kaga; Shoji Shukuri; Masahiro Moniwa; Dai Hisamoto

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