Harvey C. Hamel

An advanced multichip module (MCM) for high-performance UNIX servers

In 2001, IBM delivered to the marketplace a high-performance UNIX?®-class eServer based on a four-chip multichip module (MCM) code named Regatta. This MCM supports four POWER4 chips, each with 170 million transistors, which utilize the IBM advanced copper back-end interconnect technology. Each chip is attached to the MCM through 7018 flip-chip solder connections. The MCM, fabricated using the IBM high-performance glass-ceramic technology, features 1.7 million internal copper vias and high-density top-surface contact pad arrays with 100-?µm pads on 200-?µm centers. Interconnections between chips on the MCM and interconnections to the board for power distribution and MCM-to-MCM communication are provided by 190 meters of co-sintered copper wiring. Additionally, the 5100 off-module connections on the bottom side of the MCM are fabricated at a 1-mm pitch and connected to the board through the use of a novel land grid array technology, thus enabling a compact 85-mm ?? 85-mm module footprint that enables 8- to 32-way systems with processors operating at 1.1 GHz or 1.3 GHz. The MCM also incorporates advanced thermal solutions that enable 156 W of cooling per chip. This paper presents a detailed overview of the fabrication, assembly, testing, and reliability qualification of this advanced MCM technology.

A high density, high performance MCM-D/C package: a design, electrical, and process perspective

This paper describes a state-of-the-art seven chip MCM-D/C package currently under production for use as a processor module for the high end of IBMs AS/400 Advanced Series with PowerPC technology. Physical design, process, and electrical design (characterization) is described, and trade-offs made between them are discussed.

Electrical modeling and characterization of packaging solutions utilizing lead-free second level interconnects

This paper presents measured and modeled results of two novel lead-free interconnect solutions. A surface mounted Copper Column Grid Array (CuCGA) and a demountable Spring Land Grid Array (SLGA) will be characterized and compared to the standard Column Grid Array (CGA). The geometries and materials required for reliable connections often compete with the ones required for adequate electrical performance. To characterize the electrical performance differences, several IBM ASIC menu alumina packages were built, vatying the physical propelties of the second level interconnects for both the CuCGA and SLGA technologies. The corresponding parts were modeled and measured for loop inductance and DC resistance of the power distribution system. Excellent model to hardware correlation was achieved, and clear candidates are recommended for equivalent or better performance compared to standard CGA interconnects.

Evaluation of Cu capping alternatives for polyimide-Cu MCM-D

Among the 3 types of polyimide (PI) systems, pre-imidized, polyamic ester and polyamic acid, the latter has been shown to react with Cu surfaces when it is spun coated. This paper reviews Cu-polyimide adhesion and diffusion data and present various wet process alternatives to minimize Cu diffusion into poly(biphenyl dianhydride-p-phenylene diamine) (BPDA-PDA) polyamic acid precursor. Two different process options were investigated: a precoat or adhesion promoters (A1100, AP420 and benzotriazole) prior to the polyamic acid apply, and an additive (Tetrazole or BTA) formulated in the PAA solution. The 5 processes were compared with respect to adhesion, capacitance, dielectric constant and reliability. Only the BTA formulation had adhesion problems which were attributed to the A1100 precoat used. A1100 as a precoat was further evaluated on various copper surfaces and curing environments. All proposed solutions performed well when used on a MCM-D/C module which was used to extract electrical parametrics and was further subjected to reliability testing.

Thin film mesh: a novel approach for noise reduction in high density and high-speed single chip packages

The recent trend in microprocessor technology is for high speed devices (200-400 MHz) with a large number of simultaneously switching drivers. Other than providing the capability of packaging these devices with high signal I/O, the package also has to provide a low inductance path between the on chip drivers and decoupling capacitors. This is required for a low voltage distribution noise. In this paper, a multi-layer ceramic package with a thin film mesh structure on top of the ceramic substrate is described. Electrical analysis is presented to show that about 20% reduction in voltage distribution noise can be achieved for a high speed, high I/O device utilizing this package.