Mukta G. Farooq

3D copper TSV integration, testing and reliability

Node-agnostic Cu TSVs integrated with high-K/metal gate and embedded DRAM were used in functional 3D modules. Thermal cycling and stress results show no degradation of TSV or BEOL structures, and device and functional data indicate that there is no significant impact from TSV processing and/or proximity.

3D integration review

Abstract3-D integration delivers value by increasing the volumetric transistor density with the potential benefit of shorter electrical path lengths through use of the shorter third dimension. Several researchers have studied various aspect of 3Di such as bonding level, through silicon via processes and integration, thermomechanical reliability of the vias, and the impact of the vias on devices. In this paper, we review some of the literature with a view to understanding the key options and challenges in 3Di. We also discuss some important applications of this technology, and the constraints that have to be overcome to make it work.

Through silicon via (TSV) effects on devices in close proximity - the role of mobile ion penetration - characterization and mitigation

A new interaction between TSV processes and devices in close proximity, different from mechanical stress, is identified, studied and mitigated. Detailed characterization via Triangular Voltage Sweep (TVS) and SIMS shows the role of mobile ion penetration from BEOL layers. An improved process is presented and confirmed in test structures and DRAM.

Chip Package Interaction for 65nm CMOS Technology with C4 Interconnections

This paper discusses the chip package interaction (CPI) for a 65 nm low k BEOL CMOS chip assembled to an organic package. Inter-level dielectrics with k~3.0 and k~2.7, with oxide terminations, were used in combination with both Sn/Pb and lead-free C4s. Various underfill compounds were tested to determine their effectiveness in mitigating chip stresses without significantly impairing C4 fatigue life. A summary of the reliability stress results will be presented.

Impact of 3D copper TSV integration on 32SOI FEOL and BEOL reliability

We integrated a copper TSV (Through Silicon Via) cell in a qualified 32SOI CMOS logic technology with high-K/metal gate and DT (Deep Trench) capacitors. Extensive wafer level characterization and reliability stressing were performed to evaluate the impact of the TSVs and 3D (3-Dimensional) integration processing on device and back end of line reliability performance. This included bias temperature instability stress, hot carrier injection, thermal cycling, wiring electromigration testing, and time-dependent dielectric breakdown studies. The integration of the TSV and process shows an equivalent reliability performance with respect to the 2D baseline for FEOL (Front End of Line) and BEOL (Back End of Line) structures within the assigned 3D design rules. In particular it is demonstrated that this TSV design allows BEOL structures at zero proximity to the KOZ (Keep Out Zone). Further, device and functional data indicate that there is no change in end of life reliability targets from TSV processing and/or proximity.

Evaluation of lead(Pb)-free ceramic ball grid array (CBGA): Wettability, microstructure and reliability

Flip-chip carriers have become the preferred solution for high-performance ASIC and microprocessor devices. Typically these are packaged in organic or ceramic Ball Grid Array (BGA) packages. IBM has developed both Ceramic Ball Grid Array (CBGA) and Ceramic Column Grid Array (CCGA) packages which cover a wide range of package I/O capabilities required for high-performance devices, typically between 300 to more than 1600 I/O. Recently, there has been a lot of interest in Pb-free solders to replace typical Pb-based solders such as eutectic Sn-Pb used for balls in plastic BGAs (PBGA) for their assembly. The common feature of all proposed Pb-free solder alloys to date is that they are all Sn-based solders with the wt.% of Sn in the alloy typically greater than 90%. Antimony-based lead-free solders have been considered, but recently there has been a concern over the use of antimony (Sb) as well. The leading antimony-free (Sb-free) solder that has emerged from various Pb-free solder evaluations by industry and academic consortia at present is: 95.5Sn/3.8Ag/0.7Cu (SAC). The primary issues with changing from high-Pb based solders that are used in BGA assembly to electronic cards are: (1) wettability of the Pb-free solders to both Ni/Au I/O pads typically used in ceramic BGAs and card lands (Cu or Cu tinned with solder paste) with water soluble or no-clean fluxes; (2) the rate of intermetallic growth and its structure, with much higher Sn containing Pb-free solders; and (3) thermal fatigue reliability of the CBGA joints to organic cards. In this paper, initial assessment of a few leading Pb-free solders regarding wettability, microstructure and thermal fatigue life for CBGA applications is presented.

Spatial and temporal thermal characterization of stacked multicore architectures

Three-dimensional integration provides a new way of performance growth for microprocessor architectures. While a recent studies report promising performance improvement numbers, majority of the processor stacking options are thermally-limited. Elevated stack temperatures have significant effect on the overall energy efficiency and reliability of the processor; they also limit the potential peak performance improvement from the 3D implementation. Thermal characteristics of 3D stacks differ from 2D processors in various ways including: the nature of heat dissipation throughout the stack, thermal conductivity of the 3D structures such as micro-C4 layers, and hotspot interactions among layers. The intensity of the corresponding thermal problems is highly dependent on the 3D technology, processor and stack parameters. In this study we focus on spatial and temporal thermal characteristics of 3D multicore architectures using high-fidelity technology and processor models. Our experimental results highlight the need for integrating detailed thermal models in the design flow, starting with the early design stages. In addition, the reduced time constants and elevated on-chip temperatures indicate faster response time requirements for dynamic thermal management in processor stacking options.

Invited talk: 3D chip stacking

Summary form only given. 3D chip stacking refers to a vertical stack of chips in which individual chips can communicate with each other through electrical connections. 3D chip stacking has the ability to enhance chip performance by increasing bandwidth, reducing wire delay, and enabling better power management. In true 3D chip stacking, all chips except possibly the topmost chip, contain TSVs (Through Substrate/Silicon Vias). TSVs can be introduced into the silicon CMOS transistor fabrication at a number of points in the manufacturing sequence. Key considerations to determine the optimal introduction point include diameter of the TSV, insulating and conducting materials used in the TSV, and the technology node. TSV fabrication considerations include via etching, insulation, metallization, annealing and capping. The final structure also needs to be evaluated for thermo-mechanical integrity and reliability. Additionally, one must also consider the impact of TSVs on devices. There are different approaches to achieving 3D chip stacking, including die to die stacking, die to wafer stacking, and wafer to wafer stacking. In this talk, we will review various aspects of 3D technology, including fabrication of TSVs, and the performance and reliability of structures with TSVs. We will also review current literature to understand the unique advantages and challenges of 3D chip stacking.

Creep Characterization Of Ceramic BGA

Long term creep of a ceramic ball grid array (CBGA) solder ball under compressive loading was investigated. An experiment was conducted with two levels of loading and four of temperature. Analysis of the data assumed the composite ball structure could be simulated by an interconnection having the same shape, but of a single equivalent material. Curve fitting determined the stress exponent and activation energy of the equivalent material in the Norton creep model; the values were consistent with the range of values of the individual components available in the literature. Nonlinearity of the change in ball height with time was hypothesized to be due to geometric stiffening, a hypothesis which was confirmed by a simplified model. The model may be used to estimate creep behavior of other ball geometries having the same material set. The final result of this work - a closed form equation describing height decrease as a function of compressive force, temperature and time - can be used to simplify complex model...