Hasan M. Nayfeh

Strained silicon MOSFET technology

Mobility and current drive improvements associated with biaxial tensile stress in Si n- and p-MOSFETs are briefly reviewed. Electron mobility enhancements at high channel doping (up to 6 /spl times/ 10/sup 18/ cm/sup -3/) are characterized in strained Si n-MOSFETs. For low inversion layer carrier concentrations, channel-dopant ionized impurity scattering does reduce the strain-induced mobility enhancement, but the enhancement is recovered at higher inversion charge concentrations, where screening is efficient. Mobility enhancement in strained Si p-MOSFETs is also discussed. There are process integration challenges and opportunities associated with this technology. Dopant diffusion, and its impact on profile engineering in strained Si CMOS structures, is one example. While the slower diffusion of B in Si/sub 1-x/Ge/sub x/ enables improved doping profile control, the diffusivity of the n-type dopants is dramatically enhanced in Si/sub 0.8/Ge/sub 0.2/.

High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography

We present a 45-nm SOI CMOS technology that features: i) aggressive ground-rule (GR) scaling enabled by 1.2NA/193nm immersion lithography, ii) high-performance FET response enabled by the integration of multiple advanced strain and activation techniques, iii) a functional SRAM with cell size of 0.37mum2, and iv) a porous low-k (k=2.4) dielectric for minimized back-end wiring delay. The list of FET-specific performance elements includes enhanced dual-stress liner (DSL), advanced eSiGe, stress memorization (SMT), and advanced anneal (AA). The resulting PFET/NFET Idsat values, at Vdd of 1.0V and 45nm GR gate pitch, are 840muA/mum and 1240muA/mum respectively. The global wiring delay achieved with k=2.4 reflects a 20% reduction compared to k=3.0

A physically based analytical model for the threshold voltage of strained-Si n-MOSFETs

A physically based analytic model for the threshold voltage V/sub t/ of long-channel strained-Si--Si/sub 1-x/Ge/sub x/ n-MOSFETs is presented and confirmed using numerical simulations for a wide range of channel doping concentration, gate-oxide thicknesses, and strained-Si layer thicknesses. The threshold voltage is sensitive to both the electron affinity and bandgap of the strained-Si cap material and the relaxed-Si/sub 1-x/Ge/sub x/ substrate. It is shown that the threshold voltage difference between strained- and unstrained-Si devices increases with channel doping, but that the increase is mitigated by gate oxide thickness reduction. Strained Si devices with constant, high channel doping have a threshold voltage difference that is sensitive to Si cap thickness, for thicknesses below the equilibrium critical thickness for strain relaxation.

Influence of high channel doping on the inversion layer electron mobility in strained silicon n-MOSFETs

In this letter, we investigate the dependence of electron inversion layer mobility on high-channel doping required for sub-50-nm MOSFETs in strained silicon (Si), and we compare it to co-processed unstrained Si. For high vertical effective electric field E/sub eff/, the electron mobility in strained Si displays universal behavior and shows enhancement of 1.5-1.7/spl times/ compared to unstrained Si. For low E/sub eff/, the mobility for strained Si devices decreases toward the unstrained Si data due to Coulomb scattering by channel dopants.

Electron inversion layer mobility in strained-Si n-MOSFETs with high channel doping concentration achieved by ion implantation

Inversion layer mobility measurements in strained-Si n-MOSFETs fabricated using a typical MOSFET process including high temperature steps and with various channel doping concentrations, achieved by boron ion implantation, are compared with co-processed bulk-Si n-MOSFETs. It is found that a near-universal mobility relationship with vertical effective electric field, E/sub eff/, exists for strained-Si and bulk-Si n-MOSFETs for all channel implant doses in this study. Significant mobility enhancement for E/sub eff/ up to 2 MV/cm (1.5-1.7 x) is obtained for channel doping concentrations ranging from 10/sup 17/-6 /spl times/ 10/sup 18/ cm/sup -3/.

Advanced gate stacks with fully silicided (FUSI) gates and high-/spl kappa/ dielectrics: enhanced performance at reduced gate leakage

The key result in this work is that FUSI/HfSi/sub x/O/sub y/ gate stacks offer both significant gate leakage reduction (due to high-/spl kappa/) and drive current improvement at T/sub inv/ /spl sim/ 2 nm (due to: (i) elimination of poly depletion effect, /spl sim/ 0.5 nm, and (ii) the high mobility of HfSi/sub x/O/sub y/). We also demonstrate that threshold voltage for both PFETs and NFETs can be adjusted from midgap to the values of Vt(PFET)/spl sim/ -0.4 V and Vt(NFET) /spl sim/ + 0.3 V by poly-Si predoping by implantation (Al or As) and FUSI alloying. Significantly improved charge trapping (V/sub t/ stability) was found in the case of NiSi/ HfSi/sub x/O/sub y/ compared to the same gate electrode with HfO/sub 2/ dielectric.

Impact of ion implantation damage and thermal budget on mobility enhancement in strained-Si N-channel MOSFETs

The impact of processing factors such as ion implantation and rapid thermal annealing on mobility enhancement in strained-Si n-channel metal-oxide-semiconductor field-effect transistors (n-MOSFETs) has been investigated. Long-channel strained-Si and bulk n-MOSFETs were fabricated with various channel-region implant doses and thermal budgets. Neutral Si and Ge species were used to study the impact of the implant damage on mobility separately from ionized impurity scattering effects. Electron mobility enhancement is shown to degrade considerably when the implant dose is above a critical dose for a given thermal budget. Transmission electron microscopy, secondary ion mass spectrometry and Raman spectroscopy were used to investigate the mobility degradation mechanisms. Residual implant damage and implant damage enhanced Ge up-diffusion into the Si are shown to be responsible for the mobility degradation. Two-dimensional damage simulations of 30-nm scale MOSFETs are used to examine potential technological implications of these findings.

Effect of tensile uniaxial stress on the electron transport properties of deeply scaled FD-SOI n-type MOSFETs

In this letter, the effect of longitudinal uniaxial mechanical stress on electron mobility in high-performance fully depleted ultrathin silicon-on-insulator nFETs with a raised source/drain (RSD) architecture and channel lengths ranging from 1 /spl mu/m (long channel) to 30 nm (deeply scaled) is reported. Longitudinal uniaxial stress in the channel was achieved using a stressed nitride contact liner technique. A dR/dL method was used to minimize errors in the mobility extraction due to uncertainties in external resistance and channel length. Significant mobility enhancement of 1.6-1.8 times was achieved despite the use of an RSD and strong channel doping of roughly 5/spl times/10/sup 18/ cm/sup -3/, required for short-channel effect control.

Trade-Offs Between RF Performance and Total-Dose Tolerance in 45-nm RF-CMOS

The hot carrier and ionizing radiation responses of 45-nm SOI RF nMOSFETs are investigated. Devices with “tight” source/drain (S/D) contact spacing have improved RF performance but degraded hot carrier reliability and radiation tolerance. Devices with “loose” gate finger-to-gate finger spacing have improved RF performance and also improved hot carrier and radiation tolerance. The effects of finger width on the hot carrier stress and ionizing radiation degradation of strained silicon-on-insulator RF MOSFETs are also investigated. Enhanced degradation is observed for devices with wide finger widths and is attributed to the greater channel-region mechanical stress induced impact ionization. This result is contrary to the previous studies which showed that narrow channel width devices should exhibit greater damage. Taken together, these results have serious consequences for RF circuits that require large widths for sufficient RF gain. Finally, devices with symmetric halo doping are observed to exhibit greater total-dose degradation than devices with asymmetric halo doping.

Evaluating the Influence of Various Body-Contacting Schemes on Single Event Transients in 45-nm SOI CMOS

We investigate the single-event transient (SET) response of T-body and notched-body contacted MOSFETs from a commercial 45 nm SOI RF-CMOS technology. Although body-contacted devices suffer from reduced RF performance compared to floating body devices, previous work on 65 nm and 90 nm MOSFETs has shown that the presence of a body-contact significantly mitigates the total ionizing dose (TID) sensitivity that is exhibited in floating-body SOI MOSFETs. The influence of body-contacting schemes on the single-event effect (SEE) sensitivity is examined here through time-resolved measurements of laser and microbeam-induced transients from T-body and notched-body MOSFETs. Laser-induced transients demonstrate the reduced SEE sensitivity of the notched-body MOSFETs as compared to the T-body MOSFETs; this is evidenced by a uniform reduction in the peak transient magnitudes and collected charge for transients captured at the worst-case bias of VDS = 1.0 V, as well as with all terminals grounded. Microbeam-induced transient data are also presented to support the validity of the laser-induced transient data. Together, these data provide new insight into the RF versus TID versus SEE tradeoffs associated with body contacting schemes in nm-scale MOSFETs, an important concern for emerging space-based electronics applications.