Hassan Rabah

FPGA Implementation of Orthogonal Matching Pursuit for Compressive Sensing Reconstruction

In this paper, we present a novel architecture based on field-programmable gate arrays (FPGAs) for the reconstruction of compressively sensed signal using the orthogonal matching pursuit (OMP) algorithm. We have analyzed the computational complexities and data dependence between different stages of OMP algorithm to design its architecture that provides higher throughput with less area consumption. Since the solution of least square problem involves a large part of the overall computation time, we have suggested a parallel low-complexity architecture for the solution of the linear system. We have further modeled the proposed design using Simulink and carried out the implementation on FPGA using Xilinx system generator tool. We have presented here a methodology to optimize both area and execution time in Simulink environment. The execution time of the proposed design is reduced by maximizing parallelism by appropriate level of unfolding, while the FPGA resources are reduced by sharing the hardware for matrix-vector multiplication across the data-dependent sections of the algorithm. The hardware implementation on the Virtex6 FPGA provides significantly superior performance in terms of resource utilization measured in the number of occupied slices, and maximum usable frequency compared with the existing implementations. Compared with the existing similar design, the proposed structure involves 328 more DSP48s, but it involves 25802 less slices and 1.85 times less computation time for signal reconstruction with N = 1024, K = 256, and m = 36, where N is the number of samples, K is the size of the measurement vector, and m is the sparsity. It also provides a higher peak signal-to-noise ratio value of 38.9 dB with a reconstruction time of 0.34 μs, which is twice faster than the existing design. In addition, we have presented a performance metric to implement the OMP algorithm in resource constrained FPGA for the better quality of signal reconstruction.

Temporal partitioning methodology optimizing FPGA resources for dynamically reconfigurable embedded real-time system

Abstract In this paper we present a new temporal partitioning methodology used for the data-path part of an algorithm for the reconfigurable embedded system design. This temporal partitioning uses an assessing trade-offs in time constraint, design size and field programmable gate arrays device parameters (circuit speed, reconfiguration time). The originality of our method is that we use the dynamic reconfiguration in order to minimize the number of cells needed to implement the data-path of an application under a time constraint. Our method consists, by taking into account the used technology, in evaluating the algorithm area and operators execution time from data flow graph. Thus, we deduce the right number of reconfigurations and the algorithm partitioning for Run-Time Reconfiguration implementation. This method allows avoiding an oversizing of implementation resources needed. This optimizing approach can be useful for the design of an embedded device or system. Our approach is illustrated by various reconfigurable implementations of real time image processing data-path.

An efficient FPGA-based dynamic partial reconfiguration design flow and environment for image and signal processing IP cores

This paper describes a dynamic partial reconfiguration (DPR) design flow and environment for image and signal processing algorithms used in adaptive applications. Based on the evaluation of the existing DPR design flow, important features such as overall flexibility, application and standardised interfaces, host applications and DPR area/size placement have been taken into consideration in the proposed design flow and environment. Three intellectual property (IP) cores used in pre-processing and transform blocks of compression systems including colour space conversion (CSC), two-dimensional biorthogonal discrete wavelet transform (2-D DBWT) and three-dimensional Haar wavelet transform (3-D HWT) have been selected to validate the proposed DPR design flow and environment. Results obtained reveal that the proposed environment has a better solution providing: a scriptable program to establish the communication between the field programmable gate array (FPGA) with IP cores and their host application, power consumption estimation for partial reconfiguration area and automatic generation of the partial and initial bitstreams. The design exploration offered by the proposed DPR environment allows the generation of efficient IP cores with optimised area/speed ratios. Analysis of the bitstream size and dynamic power consumption for both static and reconfigurable areas is also presented in this paper.

Efficient architectures for 3D HWT using dynamic partial reconfiguration

This paper presents the design and implementation of three dimensional (3D) Haar wavelet transform (HWT) with transpose based computation and dynamic partial reconfiguration (DPR) mechanism on field programmable gate array (FPGA). Due to the separability property of the multi-dimensional HWT, the proposed architecture has been implemented using a cascade of three N-point one dimensional (1D) HWT and two transpose memories for a 3D volume of NxNxN suitable for real-time 3D medical imaging applications. These applications require continuous hardware servicing, hence DPR has been introduced. Two architectures were synthesised using VHDL and implemented on Xilinx Virtex-5 FPGAs. Experimental results and comparisons between different configurations using partial and non-partial reconfiguration processes and a detailed performance analysis of the area, power consumption and maximum frequency are analysed in this paper.

Simple and Efficient Compressed Sensing Encoder for Wireless Body Area Network

Compressed sensing (CS) is an emerging signal processing technique that enables sub-Nyquist measurement of signals having sparse representations in certain bases. Since most physiological signals treated within a wireless body area network (WBAN) are sparse, CS can be applied to WBANs to reduce the number of measurements and minimize the energy consumption of the sensor nodes. In this paper, we propose a simple and efficient CS encoder device used to measure signals within sensor nodes of a WBAN. A digital and an analog models of the proposed CS encoder are presented. As the CS encoder and decoder are tightly coupled, a model of the overall acquisition chain is required in the first stages of development and validation. To do this, we propose a virtual prototyping of the system with SystemC-AMS. A SPICE model and a hardware prototype of the proposed CS encoder are also presented. The simulation results of both models show that the proposed encoder was able to compressively measure an electrocardiogram (ECG) and an electroencephalogram signals with compression ratios of 6:1 and 4:1, respectively, which save 82.9% and 75% of the energy consumption of transceivers. The experiment results were consistent with those of the model and show that the hardware prototype was able to compressively measure an ECG signal with a compression ratio of 8:1. Comparison with a random demodulator (RD) was carried out and shows that the proposed encoder outperformed RD in terms of compression ratio and reconstruction quality.

Design and implementaiton of a fall detection system using compressive sensing and shimmer technology

Falls are a major problem in older adults worldwide with an estimated 30% of elderly adults over 65 years of age falling each year. Timely detection of medical emergencies can reduce treatment latency and significantly improve healthcare services. This paper presents the design and implementation of a fall detection system using compressive sensing. The proposed system is built around Shimmer technology and deploys advanced data compression technique using the orthogonal matching pursuit (OMP) algorithm. The detection approach is based on the manipulation of three axial accelerometer data acquired from the Shimmer wireless medical device and reconstructed using the OMP algorithm. The main system building blocks have been simulated and implemented on the Virtex-5 and Zynq 7 field programmable gate array (FPGA) using Vivado high level synthesis tool for system evaluation and IP core generation, area, power and computation time estimation. Results obtained have shown promising results for the detection of falls with different scenarios.

High level prototyping and FPGA implementation of the orthogonal matching pursuit algorithm

In this paper we present a novel hardware architecture for reconstruction of signals in compressed sensing. The proposed architecture is based on the orthogonal matching pursuit (OMP) algorithm which has been modeled with Simulink and implemented on FPGA using Xilinx system generator. The main aim is to optimize both area and execution time. The execution time is reduced by exploiting parallelism inside each kernel, where the area is reduced by reusing several operators such as matrix vector multiplication. Hardware implementation on the Virtex5 FPGA has shown excellent results compared to existing implementations. Moreover, our solution achieves a speedup of 38 compared to a software solution on the Intel core duo CPU.

Compressed Sensing: A Simple Deterministic Measurement Matrix and a Fast Recovery Algorithm

Compressed sensing (CS) is a technique that is suitable for compressing and recovering signals having sparse representations in certain bases. CS has been widely used to optimize the measurement process of bandwidth and power constrained systems like wireless body sensor network. The central issues with CS are the construction of measurement matrix and the development of recovery algorithm. In this paper, we propose a simple deterministic measurement matrix that facilitates the hardware implementation. To control the sparsity level of the signals, we apply a thresholding approach in the discrete cosine transform domain. We propose a fast and simple recovery algorithm that performs the proposed thresholding approach. We validate the proposed method by compressing and recovering electrocardiogram and electromyogram signals. We implement the proposed measurement matrix in a MSP-EXP430G2 LaunchPad development board. The simulation and experimental results show that the proposed measurement matrix has a better performance in terms of reconstruction quality compared with random matrices. Depending on the compression ratio, it improves the signal-to-noise ratio of the reconstructed signals from 6 to 20 dB. The obtained results also confirm that the proposed recovery algorithm is, respectively, 23 and 12 times faster than the orthogonal matching pursuit (OMP) and stagewise OMP algorithms.

Smart adaptable strain gage conditioner: hardware/software implementation

In this paper, a smart adaptable strain gage conditioning system is presented. The system is based on analog and digital processing to meet particularly adaptability, flexibility, and complex computations required in calibration and compensation algorithms of apparent strain in strain gage. Analog processing, with adequate amplification and filtering, is used to adjust the strain gage and temperature signals to the full scale of the converters. The flexibility of the digital processing is used to compute automatic calibration and temperature compensations when strain gage and spring element characteristics are known or not. This new architecture, consisting of hardware and software functionality, is implemented on an FPGA including a core processor. Description of the methodology developed for the temperature compensation of the system, the architecture implementation results, and adaptation of the system are reported.

A new ADPLL architecture dedicated to program clock references synchronization

This paper presents a totally digital phase locked loop (PLL) used for the recovery of a MPEG-2 decoder clock. The All Digital PLL (ADPLL) is implemented with a frequency synthesizer based on a new technique for phase shifting, avoiding the phase accumulation of ADPLL using a ring oscillator or avoiding the multiphase generation if a delay-locked loop (DLL) is used. The strongest point of the proposed configuration is the possibility of implementing as many ADPLLs as needed in a single circuit, in the limit of the circuit resources, without additional external circuit. The transfer characteristic, frequency resolution and jitter performance are computed and discussed. Then, the ADPLL resources and the ADPLL performances in term of time response and jitter are reported.