He Maes

Analysis of the charge pumping technique and its application for the evaluation of MOSFET degradation

It is shown that the charge pumping technique is able not only to determine the degradation mechanisms in MOS transistors under all kinds of aging conditions (e.g., irradiation, hot-carrier, Fowler-Nordheim stress), but also in several cases to evaluate and to quantify the degradation. It is further shown that the technique can be applied to separate the presence of fixed oxide changes due to charge trapping and the generation of interface traps. It can be used to analyze degradations that occur uniformly over the transistor channel, as well as strongly localized transistor degradations (e.g., for the case of hot-carrier degradations). All possible cases of uniform and nonuniform degradations, for p-channel as well as for n-channel transistors, are described, and for most of them experimental examples are given. >

Analysis and modeling of on-chip high-voltage generator circuits for use in EEPROM circuits

Most of the presently available EEPROM circuits feature 5-V-only operation and therefore incorporate on-chip high-voltage generators. In spite of the importance of these latter circuits, a thorough analysis of the circuit has not been presented. In this paper the characteristics of the voltage multiplier circuit are thoroughly analyzed and modeled. The results obtained from this analysis are fully confirmed by experiments. The degradation characteristics of the circuit are discussed and its capability to compensate for nonvolatile memory degradation is shown. >

Temperature dependence of threshold voltage in thin-film SOI MOSFETs

A first-order model for the temperature dependence of threshold voltage in thin-film silicon-on-insulator (SOI) n-MOSFETs is described. The temperature dependence of the threshold voltage of thin-film SOI n-channel MOSFETs is analyzed. Threshold voltage variation with temperature is significantly smaller in thin-film (fully depleted) devices than in thick-film SOI and bulk devices. The threshold voltage is shown to be dependent on the depletion level of the device, i.e. whether it is fully depleted or not. There exists a critical temperature below which the device is fully depleted, and above which the device operates in the thick-film regime.<<ETX>>

Evaluation of hot carrier degradation of N-channel MOSFET's with the charge pumping technique

Hot carrier degradation in n-channel MOSFET transistors has been evaluated using the charge pumping technique in addition to the conventionalI_{ds}-V_{gs}measurements. It is shown that the generation of large amounts of interface states is the primary result of moderate hot carrier stress. The simultaneous injection and recombination of injected electrons and holes is suggested to be responsible for this formation of interface states. The net charge in the oxide and interface states after any hot carrier stress is shown to be positive.

The influence of the measurement setup on enhanced AC hot carrier degradation of MOSFETs

It is shown that the enhanced degradation and substrate current component, which is observed in several AC experiments at the falling edge of the gate pulse under high drain bias, can in some cases be primarily ascribed to a carrier injection due to the forward biasing of the source diode and a simultaneous drain voltage overshoot. The forward biasing of the source diode is not caused by the commonly known latch-up effect, which is triggered by the substrate current, but by an insufficient AC coupling of the source to the ground due to the parasitic inductance of the wiring. It is demonstrated that by putting a capacitor at the drain side of the transistor and grounding the source at the probe tip, the observed enhanced substrate current can be eliminated and the anomalous enhanced degradation reduced accordingly. >

Degradation of tunnel-oxide floating-gate EEPROM devices and the correlation with high field-current-induced degradation of thin gate oxides

In the past it has been assumed that the behavior of MOS transistors and thin-oxide floating-gate memory cells during high field stress can be predicted using experimental results obtained on capacitors. Here, it is shown that, due to incorrect extrapolation of the results, important memory degradation phenomena, such as window opening, are prone to misinterpretation. The results of a study on the degradation of tunnel-oxide floating-gate EEPROM devices, making use of the charge-pumping technique in combination with threshold voltage window degradation measurements, are reported. Contacted floating-gate transistors were used to study the effect of Fowler-Nordheim tunneling on thin-oxide gate dielectrics. Different types of floating-gate transistors were subjected to different degradation conditions. By comparing the experimental results with those of a theoretical study of the influence of trapped oxide charges on injection current and threshold voltage, it is possible to explain all measured degradation characteristics unambiguously. >

A quantitative model for the conduction in oxides thermally grown from polycrystalline silicon

Oxides thermally grown from polycrystalline silicon are known to conduct much higher currents than oxides grown on monocrystalline material, which has led to their application in floating-gate electrically erasable programmable READ-only memories (EEPROM) devices (so-called textured devices) for the purpose of electrical programming and erasing of the memory device. This increased conductivity has been previously explained qualitatively by field enhancement due to the surface roughness of the polysilicon-polyoxide interfaces, but a quantitative model that could explain and predict the true injection current behavior was never proposed. In this paper, a new model is introduced, which is able to explain all of the experimental observations of conduction in polyoxides, including trapping phenomena. The new model is verified by comparison with two types of capacitor measurements. Since electron trapping in the oxide is included in the model it can also be used to investigate the degradation behavior of the textured-type floating-gate EEPROM cells. In all cases it is found that the nonuniformity of the polyoxide current strongly influences its behavior and that more specifically for EEPROM devices this nonuniformity puts severe limits on the number of program ERASE cycles that are possible.

Evaluation of channel hot carrier effects in n-MOS transistors at 77 K with the charge pumping technique

Abstract With the charge pumping technique, the role of hot holes in the channel hot carrier degradation of short channel n-MOS transistors is shown to be less pronounced at 77 K than at 300 K. Also fewer fast interface states are generated at 77 K for the same substrate current level in the low gate bias regime. Furthermore, the dominant device degradation is found to be in the high gate bias regime at 77 K, in contrast to the case of 300 K. This is due to the presence of negative charge in the oxide or in acceptor-type interface states.

On the different time dependence of interface trap generation and charge thapping during hot carrier degradation in CMOS

In this paper both I-V and charge pumping (CP) measurements are used to study the time dependence of the hot carrier degradation of n-and pMOSFETs under various stress conditions. It will be shown that for the interface trap generation, in all cases a power law relationship is obtained, while the buildup of positive and negative charge behaves logarithmically with time. The time dependence of the degradation monitored with I-V will of course be determined by the dominant degradation mechanism. in this way, the duality between the degradation of n- and pMOSFETs is confirmed. Also the relevance of these time dependencies for dynamic degradation is treated.

Understanding of the hot carrier degradation behaviour of MOSFET's by means of the charge pumping technique

Abstract In this paper the unique features of the charge pumping (CP) technique are reviewed and discussed with emphasis on their role in the evaluation and understanding of the effects and mechanisms of hot carrier degradation in MOSFETs.