Guido Groeseneken

A reliable approach to charge-pumping measurements in MOS transistors

A new and accurate approach to charge-pumping measurements for the determination of the Si-SiO2interface state density directly on MOS transistors is presented. By a careful analysis of the different processes of emission of electrons towards the conduction band and of holes towards the valence band, depending on the charge state of the interface, all the previously ill-understood phenomena can be explained and the deviations from the simple charge-pumping theory can be accounted for. The presence of a geometric component in some transistor configurations is illustrated and the influence of trapping time constants is discussed. Furthermore, based on this insight, a new technique is developed for the determination of the energy distribution of interface states in small-area transistors, without requiring the knowledge of the surface potential dependence on gate voltage.

New insights in the relation between electron trap generation and the statistical properties of oxide breakdown

In this paper it is demonstrated in a wide stress field range that breakdown in thin oxide layers occurs as soon as a critical density of neutral electron traps in the oxide is reached. It is proven that this corresponds to a critical hole fluence, since a unique relationship between electron trap generation and hole fluence is found independent of stress field and oxide thickness. In this way literature models relating breakdown to hole fluence or to trap generation are linked. A new model for intrinsic breakdown, based on a percolation concept, is proposed. It is shown that this model can explain the experimentally observed statistical features of the breakdown distribution, such as the increasing spread of the Q/sub BD/-distribution for ultrathin oxides. An important consequence of this large spread is the strong area dependence of the Q/sub BD/ for ultrathin oxides.

Analysis of the charge pumping technique and its application for the evaluation of MOSFET degradation

It is shown that the charge pumping technique is able not only to determine the degradation mechanisms in MOS transistors under all kinds of aging conditions (e.g., irradiation, hot-carrier, Fowler-Nordheim stress), but also in several cases to evaluate and to quantify the degradation. It is further shown that the technique can be applied to separate the presence of fixed oxide changes due to charge trapping and the generation of interface traps. It can be used to analyze degradations that occur uniformly over the transistor channel, as well as strongly localized transistor degradations (e.g., for the case of hot-carrier degradations). All possible cases of uniform and nonuniform degradations, for p-channel as well as for n-channel transistors, are described, and for most of them experimental examples are given. >

Consistent model for the hot-carrier degradation in n-channel and p-channel MOSFETs

A model is derived using the charge-pumping technique for the evaluation of the interface characteristics, in combination with the behavior of the drain and the substrate currents after degradation. For n-channel transistors the degradation is mainly caused by the generation of interface traps. Only in the region of hole injection (V/sub g/ approximately=V/sub t/) is the degradation dominated by the trapped holes, which mask the effect of the generated interface traps. The degradation of p-channel transistors, although completely different at first sight, occurs by the same mechanisms. For this case, the degradation is caused by trapped negative charge, which masks the influence of the interface traps. The latter are nevertheless generated in comparable amounts as in n-channel transistors. Based on these insights, improved procedures for accelerated-lifetime experiments are proposed for both channel types. Finally, the peculiar degradation behavior of n-channel transistors under alternating injection conditions is discussed and fully explained based on the static stress degradation model. >

Origin of the threshold voltage instability in SiO 2 /HfO 2 dual layer gate dielectrics

The magnitude of the V/sub T/ instability in conventional MOSFETs and MOS capacitors with SiO/sub 2//HfO/sub 2/ dual-layer gate dielectrics is shown to depend strongly on the details of the measurement sequence used. By applying time-resolved measurements (capacitance-time traces and charge-pumping measurements), it is demonstrated that this behavior is caused by the fast charging and discharging of preexisting defects near the SiO/sub 2//HfO/sub 2/ interface and in the bulk of the HfO/sub 2/ layer. Based on these results, a simple defect model is proposed that can explain the complex behavior of the V/sub T/ instability in terms of structural defects as follows. 1) A defect band in the HfO/sub 2/ layer is located in energy above the Si conduction band edge. 2) The defect band shifts rapidly in energy with respect to the Fermi level in the Si substrate as the gate bias is varied. 3) The rapid energy shifts allows for efficient charging and discharging of the defects near the SiO/sub 2//HfO/sub 2/ interface by tunneling.

A consistent model for the thickness dependence of intrinsic breakdown in ultra-thin oxides

A consistent model for the intrinsic time dependent dielectric breakdown (TDDB) of thin oxides is introduced. This model links the existing anode hole injection and the electron trap generation models together and describes wearout as a hole induced generation of electron traps. Breakdown is defined as conduction via these traps from one interface to the other. Implementing the model in a simulator, the oxide thickness dependence of the Weibull slope of the Q/sub BD/-distribution is predicted, and, using the unique relationship between hole fluence and generated electron trap density, the decrease of the critical hole fluence with oxide thickness is explained.

Impact of MOSFET gate oxide breakdown on digital circuit operation and reliability

The influence of FET gate oxide breakdown on the performance of a ring oscillator circuit is studied using statistical tools, emission microscopy, and circuit analysis. It is demonstrated that many hard breakdowns can occur in this circuit without affecting its overall function. Time-to-breakdown data measured on individual FETs are shown to scale correctly to circuit level. SPICE simulations of the ring oscillator with the affected FET represented by an equivalent circuit confirm the measured influence of the breakdown on the circuits frequency, the stand-by and the operating currents. It is concluded that if maintaining a digital circuits logical functionality is the sufficient reliability criterion, a nonzero probability exists that the circuit will remain functional beyond the first gate oxide breakdown. Consequently, relaxation of the present reliability criterion in certain cases might be possible.

Tunnel field-effect transistor without gate-drain overlap

Tunnel field-effect transistors are promising successors of metal-oxide-semiconductor field-effect transistors because of the absence of short-channel effects and of a subthreshold-slope limit. However, the tunnel devices are ambipolar and, depending on device material properties, they may have low on-currents resulting in low switching speed. The authors have generalized the tunnel field-effect transistor configuration by allowing a shorter gate structure. The proposed device is especially attractive for vertical nanowire-based transistors. As illustrated with device simulations, the authors’ more flexible configuration allows of the reduction of ambipolar behavior, the increase of switching speed, and the decrease of processing complexity.

Origin of NBTI variability in deeply scaled pFETs

The similarity between Random Telegraph Noise and Negative Bias Temperature Instability (NBTI) relaxation is further demonstrated by the observation of exponentially-distributed threshold voltage shifts corresponding to single-carrier discharges in NBTI transients in deeply scaled pFETs. A SPICE-based simplified channel percolation model is devised to confirm this behavior. The overall device-to-device ΔVth distribution following NBTI stress is argued to be a convolution of exponential distributions of uncorrelated individual charged defects Poisson-distributed in number. An analytical description of the total NBTI threshold voltage shift distribution is derived, allowing, among other things, linking its first two moments with the average number of defects per device.

Direct and Indirect Band-to-Band Tunneling in Germanium-Based TFETs

Germanium is a widely used material for tunnel FETs because of its small band gap and compatibility with silicon. Typically, only the indirect band gap of Ge at 0.66 eV is considered. However, direct band-to-band tunneling (BTBT) in Ge should be included in tunnel FET modeling and simulations since the energy difference between the Ge conduction band edges at the L and Γ valleys is only 0.14 eV at room temperature. In this paper, we theoretically calculate the parameters A and B of Kanes direct and indirect BTBT models at different tunneling directions ([100], [110], and [111]) for Si, Ge and unstrained Si1-xGex. We highlight how the direct BTBT component becomes more important as the Ge mole fraction increases. The calculation of the band-to-band generation rate in the uniform electric field limit reveals that direct tunneling always dominates over indirect tunneling in Ge. The impact of the direct transition in Ge on the performance of two realistic tunnel field-effect transistor configurations is illustrated with TCAD simulations. The influence of field-induced quantum confinement is included in the analysis based on a back-of-the-envelope calculation.