Hector Navarro

A direct bootstrapped CMOS large capacitive-load driver circuit

A new 2.5V CMOS large capacitive-load driver circuit, using a direct bootstrap technique, for low-voltage CMOS VLSI digital design is presented. The proposed driver circuit exhibits a high speed and low power consumption to drive large capacitive loads. We compare our driver structure with the direct bootstrap circuit based on Chen et al. (2002) in terms of the product of three metrics, active area, propagation time delay, and power consumption. Results demonstrate the superior performance of the proposed driver circuit.

Optical slicing of large scenes by synthetic aperture integral imaging

Integral imaging (InI) technology was created with the aim of providing the binocular observers of monitors, or matrix display devices, with auto-stereoscopic images of 3D scenes. However, along the last few years the inventiveness of researches has allowed to find many other interesting applications of integral imaging. Examples of this are the application of InI in object recognition, the mapping of 3D polarization distributions, or the elimination of occluding signals. One of the most interesting applications of integral imaging is the production of views focused at different depths of the 3D scene. This application is the natural result of the ability of InI to create focal stacks from a single input image. In this contribution we present new algorithm for this optical slicing application, and show that it is possible the 3D reconstruction with improved lateral resolution.

From the plenoptic camera to the flat integral-imaging display

Plenoptic cameras capture a sampled version of the map of rays emitted by a 3D scene, commonly known as the Lightfield. These devices have been proposed for multiple applications as calculating different sets of views of the 3D scene, removing occlusions and changing the focused plane of the scene. They can also capture images that can be projected onto an integral-imaging monitor for display 3D images with full parallax. In this contribution, we have reported a new algorithm for transforming the plenoptic image in order to choose which part of the 3D scene is reconstructed in front of and behind the microlenses in the 3D display process.

3D resolution in computationally-reconstructed integral photography

In this research we have proposed a new definition for three-dimensional (3-D) integral imaging resolution. The general concept of two-dimensional (2-D) resolution used also for 3-D is failed to describe the 3-D resolvability completely. Thus, the researches focused on resolution improvement in 3-D integral imaging systems, didnt investigate thoroughly the effect of their method on the 3-D quality. The effect has only been shown on the 2-D resolution of each lateral reconstructed image. The newly introduced 3-D resolution concept has been demonstrated based on ray patterns, the cross-section between them and the sampling points. Consequently the effect of resulting sampling points in 3-D resolvability has been discussed in different lateral planes. Simulations has been performed which confirm the theoretical statements.

Functional vector generation for combinational circuits based on data path coverage metric and mixed integer linear programming

In this paper a functional vector generation method to maximize the data path coverage of a combinational circuit is introduced. We present a new gate model based on sensitization requirements for transition propagation, and introduce a new methodology to obtain functional vectors of maximum coverage based on Mixed Integer Linear Programming (MILP). Performance comparison and results based on a large set of MCNC91 benchmark circuits are given. Experimental results show significant speedups over a greedy SAT method.

3D integral imaging monitors with fully programmable display parameters

Stereoscopic and auto-stereoscopic monitors usually produce visual fatigue in the audience due to the convergenceaccommodation conflict (the discrepancy between actual focal distance and depth perception). An attractive alternative to these technologies is integral photography (integral imaging, InI), initially proposed by Lippmann in 1908,1 and reintroduced approximately two decades ago due to the fast development of electronic matrix sensors and displays. Lippmann’s concept is that one can store the 3D image of an object by acquiring many 2D elemental images of it from different positions. This is readily achieved by using a microlens array (MLA) as the camera lens. When the elemental images are projected onto a 2D display placed in front of an MLA, the different perspectives are integrated as a 3D image. Every pixel of the display generates a conical ray bundle when it passes through the array. The intersection of many ray bundles produces a local concentration of light density that permits object reconstruction. The resulting scene is perceived as 3D by the observer, whatever his or her position relative to the MLA. Since an InI monitor truly reconstructs the 3D scene, the observation is producedwithout special goggles, with full parallax, and with no visual fatigue.2 An important challenge of projecting integral images in a monitor is the structural differences between the capture setup and the display monitor. Addressing this challenge, we have developed an algorithm that we call smart pseudoscopic-toorthoscopic conversion (SPOC). It permits the calculation of new sets of synthetic elemental images (SEIs) that are fully adapted to the display monitor characteristics. Specifically, this global pixel-mapping algorithm permits one to select the MLA Figure 1. Schematic of the experimental setup used for capturing an integral image of a 3D scene.

Fully-programmable display parameters in integral imaging by smart pseudoscopic-to-orthoscopic conversion

Previously, we reported a digital technique for formation of real, non-distorted, orthoscopic integral images by direct pickup. However the technique was constrained to the case of symmetric image capture and display systems. Here, we report a more general algorithm which allows the pseudoscopic to orthoscopic transformation with full control over the display parameters so that one can generates a set of synthetic elemental images that suits the characteristics of the Integral-Imaging monitor and permits control over the depth and size of the reconstructed 3D scene.

A geometric approach to register transfer level satisfiability

In this paper, inequalities of integer hull polyhedrons are used in mixed integer linear programming (MILP) to model the behavior of combinational subsystems, introducing a new solution for the satisfiability (SAT) problem at register transfer level (RTL). Since in these models the vertexes are located at integer positions, they can be used with linear programming (LP) to solve SAT problems. Unfortunately, when combining together several models to make up a compound RTL description, internal vertexes may appear forcing to declare one or more variables as integer. However, the use of these models inside an RTL SAT problem reduces the number of branches needed to solve the whole integer problem. Results show a CPU solution time reduction greater than one order of magnitude, growing with the size of the problem.

A one-step algorithm for finding the optimum solution of the state justification problem in RTL designs using MILP

The state justification problem is the decision problem of finding a sequence of states and input values that satisfy an output condition for a given state machine or RTL description. In such problems, there always exist optimal state sequences that require a minimum number of clock cycles to reach the desired state. As Boolean decision problems, state justification problems can be expressed as satisfiability problems (SAT) by using the time-frame expansion algorithm. Boolean SAT or BDD-based techniques are bit-level decision procedures commonly used by industrial hardware verification tools. Unfortunately, these approaches are not efficient enough, because they do not inherit the word-level information from the RTL design. Recent approaches to the SAT problem are addressed to RTL designs containing instances of both, word-level arithmetic blocks for data flow, and bit-level Boolean logic for control flow. These approaches transform the whole SAT problem for an RTL description into a mixed integer linear program (MILP). This paper presents a new approach that finds in a single step, the optimum input sequence for a given RTL description to reach a desired state. This is accomplished by applying a novel time-frame expansion method that guarantees an optimal solution and avoids performing time-frame expansions iteratively. Experimental results will demonstrate that the proposed methodology can solve any state justification problem in one step for complex FSMs. The main application of this procedure is the test pattern generation, where the main problem is to reduce the length of test sequences that verifies a microcircuit.

VESTA: a system level verification environment based on C++

System verification is an important issue to do at every design step to ensure the complete system correctness. The verification effort is becoming more time-consuming due to the increase in design complexity. New environments are necessary to reduce the complexity of this task and, most importantly, reduce the time to develop it. Among the languages used in verification, C++ is powerful enough for encapsulating the necessary concepts in a set of classes and templates. This work introduces a framework that allows describing and verifying highly complex systems in a user-friendly and speedy way with C++ classes. These encapsulate hardware description and verification concepts and can be reused throughout a project and also in various development projects. Furthermore, the resulting libraries provide an easy-to-use interface for describing systems and writing test benches in C++, with a transparent connection to an HDL simulator. VESTA includes an advanced memory management with an extremely versatile linked list. The linked list access mode can change on-fly to a FIFO, a LIFO or a memory array access mode, among others. Experimental results demonstrate that the basic types provided by our verification environment excel the features of non-commercial solutions as Openvera or TestBuilder and commercial solutions such as e language. Besides, the results achieved have shown significant productivity gain in creating reusable testbenches and in debugging simulation runs.