Javier Sosa

A direct bootstrapped CMOS large capacitive-load driver circuit

A new 2.5V CMOS large capacitive-load driver circuit, using a direct bootstrap technique, for low-voltage CMOS VLSI digital design is presented. The proposed driver circuit exhibits a high speed and low power consumption to drive large capacitive loads. We compare our driver structure with the direct bootstrap circuit based on Chen et al. (2002) in terms of the product of three metrics, active area, propagation time delay, and power consumption. Results demonstrate the superior performance of the proposed driver circuit.

Low power voltage limiter design for a full passive UHF RFID sensor

This paper presents a low power voltage limiter design that avoids possible damages in the circuits of the analog front-end of the RFID sensor due to voltage surges whenever reader and tag are very close. The proposed voltage limiter design takes advantage of the implemented bandgap reference and voltage regulator in order to provide low temperature and process deviation of the limiting voltage. The measured limiting voltage is 2.9V with a voltage variation of only +/−0.025V for the four measured dies. The current consumption is only 150nA when the reader and the tag are far away one to each other, not limiting the sensitivity of the tag due to an undesired consumption in the voltage limiter. The circuit is implemented on a low cost 2P4M 0.35µm CMOS technology.

Design and Optimization of a Low Power Pressure Sensor for Wireless Biomedical Applications

A blood pressure sensor suitable for wireless biomedical applications is designed and optimized. State-of-the-art blood pressure sensors based on piezoresistive transducers in a full Wheatstone bridge configuration use low ohmic values because of relatively high sensitivity and low noise approach resulting in high power consumption. In this paper, the piezoresistance values are increased in order to reduce by one order of magnitude the power consumption in comparison with literature approaches. The microelectromechanical system (MEMS) pressure sensor, the mixed signal circuits signal conditioning circuitry, and the successive approximation register (SAR) analog-to-digital converter (ADC) are designed, optimized, and integrated in the same substrate using a commercial 1 μm CMOS technology. As result of the optimization, we obtained a digital sensor with high sensitivity, low noise (0.002 μV/Hz), and low power consumption (358 μW). Finally, the piezoresistance noise does not affect the pressure sensor application since its value is lower than half least significant bit (LSB) of the ADC.

Digital output MEMS pressure sensor using capacitance-to-time converter

In this paper, a MEMS capacitive pressure sensor and a capacitance to digital converter are presented. The MEMS transducer has been designed and fabricated using MetalMUMPs process from MEMSCAP. For an diaphragm area of 600×600 μm2 and an electrostatic pressure variation up to 30 kPa, the MEMS exhibits a capacitance change from 9.3 pF to 13.4 pF, with a INL of 0.2% A capacitance to digital converter has been designed and fabricated in a low cost 2P4M 0.35μm CMOS standard process as a digital interface to the MEMS sensor. The measured resolution of 7.9 bit and power consumption of 16.56 μW demonstrate that by combining both devices a long range passive RFID sensor for pressure measurements up to 30 kPa is achieved.

Gains tuning of a PI-Fuzzy controller by genetic algorithms

Purpose – Nowadays, in order to improve current applications, industry incorporates to their solution approaches artificial intelligence techniques and methodologies like Fuzzy Logic, neural networks and/or genetic algorithms (GA). Artificial intelligence techniques complement classical methodologies and include concepts that simulate the way humans solve problems or how processes work in nature. In this work, the Fuzzy Logic system cancels the effects of load perturbances in an energy plant, by implementing a secondary controller which complements the main controller. The purpose of this paper is to use GA to tune this new secondary controller. The authors particularize the proposal for three specific applications: control the angular speed and position of a Direct Current (DC) motor and control the output voltage of a DC/DC buck converter. Design/methodology/approach – The authors use GA for tuning a Proportional-Integral Fuzzy Controller (PI-Fuzzy). The proposal defines a new objective function in comp...

Low-power MEMS pressure sensor for wireless biomedical applications

Reducing power consumption leads to improve wireless sensor autonomy, increase battery life, and reduce radiated power. State-of-the-art blood pressure sensors based on piezoresistive transducers in a full Wheatstone bridge configuration uses low ohmic values because high sensitivity and low noise approach. In this work, the piezoresistance values are increased in order to reduce one order of magnitude the power consumption. The noise introduced by this improvement was proved that does not limit the accuracy for 8-bit applications. Therefore, a low power consumption pressure sensor with high sensitivity and low noise is proposed. Power consumption versus sensitivity tradeoff is analyzed in detail.

High performance single supply CMOS inverter level up shifter for multi: supply voltages domains

A single supply CMOS inverter level shifter (ssqc- ls) for upconverting signals from 0.4V-1V logic level range up to 1.1V power supply domain is introduced. For guaranteing a low energy consumption, the proposed shifter is based on topological modifications of the structure qc-level shifter reported in [1]. For 0.5V input square wave switching at 500MHz, the inverter level shifter ssqc-ls using 1.2V of power supply voltage achieves a 60% of Figure of Merit improvement in comparison against jy-ls [8] with a dual power supply voltage of 0.6V and 1.2V. Post-layout simulation results shown that ssqc-ls reaches a propagation delay of 0.75ns, an energy consumption of only 2.3pJ, and an energy- delay product of 1.73pJns for a capacitive loading condition of 950fF.

High performance dual supply level up/down shifter for a 0.6V–1V input/output range and 1.2V output/input

This paper proposes some important contributions in the design of a low voltage and low energy consumption CMOS level up shifter (bqc-ls) as well as to obtain a high performance level down shifter (bqc-ls/rev) based on the structure presented in [1]. The novel level up/down shifters are suitable for multiple clocks and different supply voltages domain logic systems with minimal area and energy consumption. When the pre-layout simulation is realized with UMC 65nm CMOS technology using regular threshold voltage transistors for a high capacitive load (2pF), the active area and the energy-delay product of bqc-ls are lower than that of reported level shifters. However, the layout of bqc-ls and bqc-ls/rev were implemented using low threshold voltage transistors, because the parasitic capacitance by the layout implementation, the maximum capacitive loading condition is 450fF. Even in this case our proposed circuits are very effective for low voltage operation and low energy consumption. The topology of bqc-ls/rev (level down shifter) is equal than that of bqc-ls, and the only difference between them is the size of their output inverter. Thus the active area for bqc-ls/rev is only 2.6% higher than that required for bqc-ls (level up shifter).

Bootstrapped Adiabatic Complementary Pass-Transistor Logic Driver Circuit for Large Capacitive Load and Low-energy Applications

This paper presents the design of an adiabatic/bootstrapped CMOS driver (xb–ad) using complementary pass–transistor logic (CPL) and a four–phase power clock. The proposed xb–ad uses a bootstrapped load driven circuit with PMOS and NMOS transistors driven by an NMOS evaluation logic block. When implemented on a 65nm CMOS 1V technology, under the large capacitive loading condition (16pF), xb–ad performs better than the reference adiabatic circuit (cpl–ad) in terms of active area (64%), and energy– delay product (39%). Moreover, xb–ad supports 10 times higher output capacitive load without any additional circuit sizing than cpl–ad. Keywords-adiabatic circuit; bootstrap capacitor; energy– recovery; high capacitive load; low–voltage

Multi-objective genetic algorithms applied to low power pressure microsensor design

Purpose – The purpose of this paper is to explain in detail the optimization of the sensitivity versus the power consumption of a pressure microsensor using multi-objective genetic algorithms. Design/methodology/approach – The tradeoff between sensitivity and power consumption is analyzed and the Pareto frontier is identified by using NSGA-II, AMGA-II and ɛ-MOEA methods. Findings – Comparison results demonstrate that NSGA-II provides optimal solutions over the entire design space for spread metric analysis, and AMGA-II is better for convergence metric analysis. Originality/value – This paper provides a new multiobjective optimization tool for the designers of low power pressure microsensors.