Juan A. Montiel-Nelson

Analysis of High-Performance Fast Feedthrough Logic Families in CMOS

This brief presents a new CMOS logic family using the feedthrough evaluation concept and analyzes its sensitivity against technology parameters for practical applications. The feedthrough logic (FTL) allows for a partial evaluation in a computational block before its input signals are valid, and does a quick final evaluation as soon as the inputs arrive. The FTL is well suited to arithmetic circuits where the critical path is made of a large cascade of inverting gates. Furthermore, FTL based circuits perform better in high fanout and high switching frequencies due to both lower delay and dynamic power consumption. Experimental results, for practical circuits, demonstrate that low-power FTL provides for smaller propagation time delay (4.1 times), lower energy consumption (35.6%), and similar combined delay, power consumption and active area product (0.7% worst), while providing lower sensitivity to power supply, temperature, capacitive load and process variations than the standard CMOS technologies.

A direct bootstrapped CMOS large capacitive-load driver circuit

A new 2.5V CMOS large capacitive-load driver circuit, using a direct bootstrap technique, for low-voltage CMOS VLSI digital design is presented. The proposed driver circuit exhibits a high speed and low power consumption to drive large capacitive loads. We compare our driver structure with the direct bootstrap circuit based on Chen et al. (2002) in terms of the product of three metrics, active area, propagation time delay, and power consumption. Results demonstrate the superior performance of the proposed driver circuit.

A CORDIC processor for FFT computation and its implementation using gallium arsenide technology

In this paper, the architecture and the implementation of a complex fast Fourier transform (CFFT) processor using 0.6 /spl mu/m gallium arsenide (GaAs) technology are presented. This processor computes a 1024-point FFT of 16 bit complex data in less than 8 /spl mu/s, working at a frequency beyond 700 MHz, with a power consumption of 12.5 W. The architecture of the processor is based on the COordinate Rotation DIgital Computer (CORDIC) algorithm, which avoids the use of conventional multiplication-and-accumulation (MAC) units, but evaluates the trigonometric functions using only add and shift operations, Improvements to the basic CORDIC architecture are introduced in order to reduce the area and power of the processor. This together with the use of pipelining and carry save adders produces a very regular and fast processor, The CORDIC units were fabricated and tested in order to anticipate the final performance of the processor. This work also demonstrates the maturity of GaAs technology for implementing ultrahigh-performance signal processors.

A Single-Capacitor Bootstrapped Power-Efficient CMOS Driver

A high speed and low power driver employing a single bootstrap capacitor is reported. It provides a six-fold improvement in the power dissipation, 15% higher speed, and 8.7% reduction in the active area when compared with the fastest reported driver (Chen et al., 2003) using bootstrap techniques, under similar loading conditions and circuit parameters

Adaptive Low/High Voltage Swing CMOS Driver for On-Chip Interconnects

This paper reports the design of a high performance, adaptive low/high swing CMOS driver circuit (mj-driver) suitable for driving of global interconnects with large capacitive load. When implemented on 0.13mum CMOS technology, mj-driver performs 16% faster, reduces the power consumption by 3%, and energy delay product by 19% when compared with a counterpart driver in diode-connected configuration. On the other hand, mj-driver has 47% lower active area and only requires one set of sizing for optimum performance at 1 and 0.8V. Furthermore, unlike its counter part which exhibits 30% variation in output swing voltage with variation in the load, the output voltage swing for the proposed driver remains unchanged with the output load. Comparisons of the proposed driver with conventional full swing CMOS driver are presented as well, indicating a significant saving in energy, due to the reduced swing voltage. The proposed driver has the ability to switch from a low swing to high swing mode, through a line monitoring mechanism

Bootstrapped full-swing CMOS driver for low supply voltage operation

This paper reports a high speed and low power consumption direct-indirect bootstrapped full-swing CMOS inverter driver circuit (bfi-driver). The simulation results, based on 0.13mum triple well CMOS technology, show that, when operated at IV, bfi-driver is 94% faster and consumes 22% less power compared to a counterpart direct bootstrap circuit (Bellaour, 1995)

Fast feedthrough logic: a high performance logic family for GaAs

A GaAs dynamic logic family using the feedthrough evaluation concept is presented in this paper. Feedthrough logic (FTL) allows the outputs to be partially generated before the input signals arrive. A modified version of this logic, where the function and its complement are implemented in a differential structure, is also introduced. In an FTL gate, the logic outputs are reset to low during the high phase of the clock and evaluated during the low phase of the clock. Resetting to low alleviates the problems of charge sharing and leakage current associated with the other GaAs dynamic logic families. FTL logic functions can be cascaded in a domino-like fashion without a need for the intervening inverters. We employ this novel concept to design several arithmetic circuits. We compare a 4-bit ripple carry adder in FTL with the other published works in terms of device count, area, delay, clock rate and power consumption. The results demonstrate that FTL is the simplest, the fastest, and consumes least power. In addition, our FTL design compares very well with the standard CMOS technology. FTL gates are fully compatible with direct coupled field-effect transistor logic (DCFL), and therefore, can be included in a DCFL standard cell library for improving cell-based ASIC performance. To match the high-speed of the FTL combinational blocks, we present a single-ended latch for pipelining the FTL blocks. Comparisons with the other published results demonstrate the superior performance of our dynamic latch.

CMOS Driver-Receiver Pair for Low-Swing Signaling for Low Energy On-Chip Interconnects

This paper describes the design of symmetric low-swing driver-receiver pairs (mj-sib) and (mj-db) for driving signals on the global interconnect lines. The proposed signaling schemes were implemented on 1.0 V 0.13-mum CMOS technology, for signal transmission along a wire-length of 10 mm and the extra fan-out load of 2.5 pF (on the wire). The mj-sib and mj-db schemes reduce delay by up to 47% and 38% and energy-delay product by up to 34% and 49%, respectively, when compared with other counterpart symmetric and asymmetric low-swing signaling schemes. The other key advantages of the proposed signaling schemes are that they require only one power supply and threshold voltage, hence significantly reducing the design complexity. This paper also confirms the relative reliability benefits of the proposed signaling techniques through a signal-to-noise ratio (SNR) analysis.

High performance CMOS dual supply level shifter for a 0.5V input and 1V output in standard 1.2V 65nm technology process

This paper presents the design of a highly efficient CMOS level shifter qc-level shifter. Unlike many recent level shifters, the proposed qc-level shifter does not use bootstrap capacitors to minimize active area. When implemented on a 65nm CMOS technology, under the large capacitive loading condition (2pF), qc-level shifter has a lower active area (94%), and energy-delay product (21.4%) than the reference bootstrap level shifter circuit (ts-level shifter). In comparison to a conventional shifter (c-level shifter)the corresponding reductions are 9.5% and 55%, respectively. Also qc-level shifter has very small effective input capacitance in comparison with ts-level shifter as it does not need a bootstrap capacitor connected to its input.

High performance bootstrapped CMOS low to high-swing level-converter for on-chip interconnects

This paper proposes a high performance and low power bootstrapped CMOS level-converter (lf-converter) for level restoration from the low-swing on the interconnect line to high-swing at the receiver side. The proposed lf-converter reduces the power-delay product by 83% to 90%, in comparison with the previously reported bootstrapped level-converter circuit (lrc-converter), when implemented on 0.13 mum CMOS 1.2V technology. The active area for lf-converter is 18.7 mum2, which is 3.9% less than the counterpart lrc-converter circuit.