Jose C. Garcia

A direct bootstrapped CMOS large capacitive-load driver circuit

A new 2.5V CMOS large capacitive-load driver circuit, using a direct bootstrap technique, for low-voltage CMOS VLSI digital design is presented. The proposed driver circuit exhibits a high speed and low power consumption to drive large capacitive loads. We compare our driver structure with the direct bootstrap circuit based on Chen et al. (2002) in terms of the product of three metrics, active area, propagation time delay, and power consumption. Results demonstrate the superior performance of the proposed driver circuit.

A Single-Capacitor Bootstrapped Power-Efficient CMOS Driver

A high speed and low power driver employing a single bootstrap capacitor is reported. It provides a six-fold improvement in the power dissipation, 15% higher speed, and 8.7% reduction in the active area when compared with the fastest reported driver (Chen et al., 2003) using bootstrap techniques, under similar loading conditions and circuit parameters

Adaptive Low/High Voltage Swing CMOS Driver for On-Chip Interconnects

This paper reports the design of a high performance, adaptive low/high swing CMOS driver circuit (mj-driver) suitable for driving of global interconnects with large capacitive load. When implemented on 0.13mum CMOS technology, mj-driver performs 16% faster, reduces the power consumption by 3%, and energy delay product by 19% when compared with a counterpart driver in diode-connected configuration. On the other hand, mj-driver has 47% lower active area and only requires one set of sizing for optimum performance at 1 and 0.8V. Furthermore, unlike its counter part which exhibits 30% variation in output swing voltage with variation in the load, the output voltage swing for the proposed driver remains unchanged with the output load. Comparisons of the proposed driver with conventional full swing CMOS driver are presented as well, indicating a significant saving in energy, due to the reduced swing voltage. The proposed driver has the ability to switch from a low swing to high swing mode, through a line monitoring mechanism

Bootstrapped full-swing CMOS driver for low supply voltage operation

This paper reports a high speed and low power consumption direct-indirect bootstrapped full-swing CMOS inverter driver circuit (bfi-driver). The simulation results, based on 0.13mum triple well CMOS technology, show that, when operated at IV, bfi-driver is 94% faster and consumes 22% less power compared to a counterpart direct bootstrap circuit (Bellaour, 1995)

High performance CMOS dual supply level shifter for a 0.5V input and 1V output in standard 1.2V 65nm technology process

This paper presents the design of a highly efficient CMOS level shifter qc-level shifter. Unlike many recent level shifters, the proposed qc-level shifter does not use bootstrap capacitors to minimize active area. When implemented on a 65nm CMOS technology, under the large capacitive loading condition (2pF), qc-level shifter has a lower active area (94%), and energy-delay product (21.4%) than the reference bootstrap level shifter circuit (ts-level shifter). In comparison to a conventional shifter (c-level shifter)the corresponding reductions are 9.5% and 55%, respectively. Also qc-level shifter has very small effective input capacitance in comparison with ts-level shifter as it does not need a bootstrap capacitor connected to its input.

High performance bootstrapped CMOS low to high-swing level-converter for on-chip interconnects

This paper proposes a high performance and low power bootstrapped CMOS level-converter (lf-converter) for level restoration from the low-swing on the interconnect line to high-swing at the receiver side. The proposed lf-converter reduces the power-delay product by 83% to 90%, in comparison with the previously reported bootstrapped level-converter circuit (lrc-converter), when implemented on 0.13 mum CMOS 1.2V technology. The active area for lf-converter is 18.7 mum2, which is 3.9% less than the counterpart lrc-converter circuit.

Efficient CMOS driver-receiver pair with low-swing signaling for on-chip interconnects

This paper describes the design of a symmetric low-swing driver-receiver pair (mj-sib) for driving signals on the global interconnect lines. When implemented on a 0.13 mum CMOS 1.2 V technology, mj-sib scheme reduces energy-delay product by 41.7% (at the receiver load of 0.25 pF) and has 38.8% lower delay when compared with a counterpart asymmetric low-swing signaling scheme. Also, mj-sib topology has 14.2% lower energy-delay product and has 36% lower active area (50.25 mum2) when compared with other symmetric low-swing signaling structure. The key advantages of the proposed signaling scheme is that it requires only one power supply and threshold voltage, hence significantly reducing the design complexity.

A single capacitor bootstrapped power efficient CMOS driver

A high-speed and low-power driver employing a single bootstrap capacitor is reported. It outperforms the other CMOS bootstrap drivers in terms of power dissipation, performance, and active area, under the similar loading conditions and circuit parameters, when implemented in the triple-well 0.13-mum CMOS process from UMC

Analysis and comparison of high performance CMOS adiabatic drivers

This paper presents the design and comparative evaluation of four low energy CMOS adiabatic drivers; ib-drive using a dual-rail structure with complementary input and output; scal-driver using a single input stage based on a single transistor driving a pair of cross-coupled CMOS inverters; ob-driver using an output stage with two inverters driven by a pre-driver circuit consisting of two differential cascode voltage switch (DCVS) logic cells; ee-driver using an output stage with two bootstrap capacitors driven by a pre-driver circuit consisting of two differential cascode voltage switch (DCVS) logic cells. When implemented on a 0.13µm CMOS 1.0V technology, ib-driver performs better than the other adiabatic circuits, in terms of the energy-delay product by up to 68%.

A CMOS adiabatic inverter operating with a single clock power supply to reduce non-adiabatic loss

This paper presents the design of a low energy CMOS adiabatic inverter (Ib-driver). The proposed Ib-driver structure uses complementary input, output and a dual-rail structure. When implemented on a 0.13 mum CMOS 1.2 V technology, under the large capacitive loading condition, Ib-driver performs better than the reference adiabatic circuit (sk-driver) in terms of the energy-delay product (21%), with active area which is (34%) lower. Proposed inverter has a full swing for high capacitive loads (20 pF).