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Charge trapping properties of the HfO2 layer with various thicknesses for charge trap flash memory applications

MHOS (metal-HfO2–SiO2–Si) structure capacitors were fabricated to investigate the charge trapping properties of HfO2 layer with various thicknesses for the applications of charge trap flash (CTF) memory devices. Also, the centroid of charge trap in HfO2 layer was extracted by constant current stress method and compared with that of conventional Si3N4 layer. The gate leakage current of MHOS capacitor due to tunneling was significantly reduced by stacking the HfO2 trap layer on thin SiO2 tunnel layer. The MHOS capacitors showed a larger memory window than the MNOS (metal-Si3N4–SiO2–Si) capacitors at the same trap layer thickness, because the HfO2 layer has better charge trapping efficiency than the Si3N4 layer. It is found that ultrathin HfO2 trap layer with a thickness of 2 nm stored almost the same charges with Si3N4 layer with a thickness of 7 nm. Consequently, the application of ultrathin HfO2 to charge storage layer can considerably improve the performance and enhance the high density of CTF memory.

Structural and electrical properties of low temperature sintered Li2CO3 doped (Ba,Sr)TiO3 ceramics

In this paper, we present the results of the fabrication and characterization of Li2CO3 doped (Ba,Sr)TiO3 ceramics for the low temperature sintering processes. In these days, low temperature sintering process has been widely spread out for the integrated electronic modules for the communication systems such as front-end modules, antenna modules, and switching modules. Generally it is believed that low temperature sintering process can be applied to the functional materials if they can be sintered less than 900 °C. However, BaSrTiO3 materials for the tunable microwave devices applications have relatively high sintering temperature of 1350 °C. Therefore, in this study to obtain low sintering temperature, we have added 1–5 wt % of Li2CO3 to BaSrTiO3 materials to reduce the sintering temperature from 1350 to around 900 °C.

Low operation voltage and high thermal stability of a WSi2 nanocrystal memory device using an Al2O3/HfO2/Al2O3 tunnel layer

A WSi2 nanocrystal nonvolatile memory device was fabricated with an Al2O3/HfO2/Al2O3 (AHA) tunnel layer and its electrical characteristics were evaluated at 25, 50, 70, 100, and 125 °C. The program/erase (P/E) speed at 125 °C was approximately 500 μs under threshold voltage shifts of 1 V during voltage sweeping of 8 V/−8 V. When the applied pulse voltage was ±9 V for 1 s for the P/E conditions, the memory window at 125 °C was approximately 1.25 V after 105 s. The activation energies for the charge losses of 5%, 10%, 15%, 20%, 25%, 30%, and 35% were approximately 0.05, 0.11, 0.17, 0.21, 0.23, 0.23, and 0.23 eV, respectively. The charge loss mechanisms were direct tunneling and Pool-Frenkel emission between the WSi2 nanocrystals and the AHA barrier engineered tunneling layer. The WSi2 nanocrystal memory device with multi-stacked high-K tunnel layers showed strong potential for applications in nonvolatile memory devices.

LOW TEMPERATURE SINTERING OF Li2CO3 ADDED (Ba,Sr)TiO3 CERAMICS

ABSTRACT In this paper, we present the results of the fabrication and characterization of Li2CO3 doped (Ba, Sr)TiO3 ceramics for the low temperature sintering processes. In these days, low temperature sintering process has been widely spread out for the integrated electronic modules for the communication systems such as front-end modules, antenna modules, and switching modules. Generally it is believed that low temperature sintering process can be applied to the functional materials if they can be sintered less than 900°C. However, BaSrTiO3 materials for the tunable microwave devices applications have relatively high sintering temperature of 1350°C. Therefore, in this study to obtain low sintering temperature, we have added 1∼5 wt % of Li2CO3 to BaSrTiO3 materials to reduce sintering temperature from 1350°C to around 900°C. In this paper, we will report the crystalline and electrical properties of Li2CO3 added BaSrTiO3 materials for the low sintering temperature applications.

Nonvolatile Poly-Si TFT Charge-Trap Flash Memory With Engineered Tunnel Barrier

Tunnel-barrier-engineered thin-film transistor (TFT) memory (TBE-TFT memory) devices on glass substrates were fabricated using low-temperature processes. An amorphous silicon film on the glass substrate was crystallized using excimer laser annealing for system-on-panel applications. The engineered tunnel barrier of VARIOT type (SiO₂/Si₃N₄/SiO₂) with a high-<i>k</i> HfO₂ charge-trapping layer and an Al₂O₃ blocking layer was applied to TBE-TFT memory devices in order to enhance the memory performance of TBE-TFT memory devices. As a result, the poly-Si TFT charge-trap Flash memory with an engineered tunnel barrier exhibited excellent memory characteristics, such as large memory window (9.5 V), long retention time, and endurance.

Electrical Characteristics of WSi2 Nanocrystal Capacitors with Barrier-Engineered High-k Tunnel Layers

Nanocrystal-floating gate capacitors with WSi2 nanocrystals and high-k tunnel layers were fabricated to improve the electrical properties such as retention, programming/erasing speed, and endurance. The WSi2 nanocrystals were distributed uniformly between the tunnel and control gate oxide layers. The electrical performance of the tunnel barrier with the SiO2/HfO2/Al2O3 (2/1/3 nm) (OHA) tunnel layer appeared to be better than that with the Al2O3/HfO2/Al2O3 (2/1/3 nm) (AHA) tunnel layer. When ΔVFB is about 1 V after applying voltage at ±8 V, the programming/erasing speeds of AHA and OHA tunnel layers are 300 ms and 500 µs, respectively. In particular, the device with WSi2 nanocrystals and the OHA tunnel barrier showed a large memory window of about 7.76 V when the voltage swept from 10 to -10 V, and it was maintained at about 2.77 V after 104 cycles.

SIMULATION AND FABRICATION OF EMBEDDED CAPACITORS FOR ORGANIC-BASED RF SYSTEM ON PACKAGE APPLICATIONS

ABSTRACT Embedded capacitor technology is one of the effective packing technologies for small size, high reliability, high performance and low cost of electric packaging systems. In this paper, the embedded capacitors were simulated and fabricated in the 8-layered printed circuit board employing standard PCB processes for RF SOP (System on package) applications. Usually, to reduce the size of embedded capacitors, high dielectric constant composites materials were employed. The composites of barium titanante (BaTiO3) powder and epoxy resin were employed in the dielectric materials for embedded capacitor applications. Theoretical considerations regarding the embedded capacitors have been paid to understand the frequency dependent impedance behavior. Frequency dependent impedance of fabricated embedded capacitors was investigated. Parasitic inductance was developed mainly through via holes and it has almost same value for all capacitors. Frequency dependent capacitance values of fabricated embedded capacitors were well matched with those of simulated embedded capacitors. Temperature dependent capacitance and loss tangent of fabricated embedded capacitor were presented.

Comparative Analysis of Li2CO3 Doped (Ba,Sr)TiO3 and ZnBO Doped (Ba,Sr)TiO3 Ceramics for the Low Temperature Sintering Applications

For the research on the LTCC(Low Temperature Co-fire Ceramic) applications, low temperature sintered ceramics have been extensively investigated. In this study, we have focused on the Li 2 CO 3 doped (Ba,Sr)TiO 3 and ZnBO doped (Ba,Sr)TiO 3 ceramics which have moderate dielectric properties such as high dielectric permittivity and low loss tangent. Until now, B 2 O 3 has been commonly employed as the low temperature sintering aid. However, in this paper, we suggest Li 2 CO 3 and ZnBO as alternative sintering aids to the B 2 O 3 . 1∼5 wt% of Li 2 CO 3 or ZnBO was added to BST ceramics in order to reduce the sintering temperature. Li 2 CO 3 doped BST and ZnBO doped BST ceramics were respectively sintered from 700°C to 1050°C and 750°C to 1250°C by 50°C to confirm the sintering temperature with different dopants concentrations. By adding Li 2 CO 3 to the BST ceramics, the sintering temperature of BST ceramics was drastically lowered down to 900°C, whereas by introducing ZnBO dopants to BST, the loss tangent was decreased. From the XRD analysis, ZnBO doped BST ceramics have no pyro phase. 3 wt% Li 2 CO 3 doped BST ceramics, which sintered at 900°C, have moderate relative dielectric permittivity of 1451 at 1 kHz, while 5 wt% ZnBO doped BST ceramics, sintered at 1100°C, have decreased dielectric permittivity of 1180 at 1 kHz. The loss tangent of ZnBO doped BST was decreased compared with that of BST. The loss tangent of ZnBO (1 wt%) doped BST was decreased down to 2.71 × 10−3 at 1 MHz.

Simulation and Fabrication of Embedded Capacitors in the Multilayer Printed Circuit Board

Embedded system technology can improve electrical performance and reduce assembly cost compared with those discrete component technologies. In this paper, simulation and characterization of embedded capacitors will be presented. The embedded capacitors were simulated and characterized employing eight layered printed circuit boards. Fabrication process of multilayer embedded capacitors will be presented. Theoretical considerations regarding the embedded capacitors have been paid to understand the frequency dependent impedance behavior. Frequency dependent impedances, capacitances, and quality-factors of fabricated embedded capacitors were investigated. As a result, parasitic inductance was developed mainly through via holes and it has almost same value regardless of different capacitances. Frequency dependent capacitance values of fabricated embedded capacitors were well matched with those of simulated embedded capacitors. Temperature dependent capacitance and loss tangent of fabricated embedded capacitor were presented.

Speed Enhancement of WSi2 Nanocrystal Memory with Barrier-Engineered Si3N4/HfAlO Tunnel Layer

WSi2 nanocrystal nanofloating gate capacitors with multistacked Si3N4/HfAlO high-k tunnel layers were fabricated and their electrical properties were characterized. The thicknesses of the Si3N4 and HfAlO tunnel layers were 1.5 and 3 nm, respectively. The asymmetrical Si3N4/HfAlO tunnel layer was modulated to enhance the tunneling efficiency to improve program and erase speeds. The flat-band voltage shift of the WSi2 nanofloating gate capacitor was about 7.2 V after applied voltages swept were from -10 to 10 V and from 10 to -10 V. Then, the program/erase speeds and the memory window under programming and erasing at ±7 V were 300 µs and 1 V, respectively. As demonstrated in the results, the WSi2 nanocrystal memory with barrier-engineered Si3N4/HfAlO layers could be applied to enhance the program and erase speeds at low operating voltages for nanocrystal nonvolatile memory application.