Hem M. Vaidya

Merged 2.5-V and 3.3-V 0.25-μm CMOS technology

In this paper a merged 2.5 V and 3.3 V high performance 0.25 micrometer CMOS technology is presented. Issues relevant to manufacturing, such as Leff control and the impact of plasma-assisted back-end dielectric depositions on gate oxide reliability and isolation, are discussed. This technology features a 50 angstrom gate oxide, high-energy implant scheme, n+-polysilicon gate, and 4/5 levels of metal. An improvement of 1.45X in circuit performance and 4X in packing density is achieved over our 0.35 micrometer CMOS technology. The nominal ring oscillator delay time is 38(39) ps for 3.3(2.5) V operation.