Isik C. Kizilyalli

Deuterium post-metal annealing of MOSFET's for improved hot carrier reliability

Low-temperature post-metallization anneals in hydrogen ambients are critical to CMOS fabrication technologies in reducing Si/SiO/sub 2/ interface trap charge densities by hydrogen passivation. In this letter we show that the hot carrier reliability (lifetime) of NMOS transistors can be increased by an order of magnitude when wafers are annealed in a deuterium ambient. This phenomenon can be understood as a kinetic isotope effect. The chemical reaction rates involving the heavier isotopes are reduced, and consequently, under hot electron stress, bonds to deuterium are more difficult to break than bonds to protium (H). However, the static chemical bonding (i.e., binding energies and excited states) is evidently the same for both hydrogen and deuterium. We measure identical transistor function after hydrogen and deuterium treatment before hot electron dynamics and resultant damage. Therefore, deuterium and hydrogen post-metal anneal processes are compatible with each other in semiconductor manufacturing. SIMS analysis proves that at typical anneal temperatures (400-450/spl deg/C), deuterium diffuses rapidly through the interlevel oxides and accumulates at Si/SiO/sub 2/ interfaces. Transistor speed versus reliability trade-off in CMOS device design is discussed in light of the findings of this study.

MOS transistors with stacked SiO/sub 2/-Ta/sub 2/O/sub 5/-SiO/sub 2/ gate dielectrics for giga-scale integration of CMOS technologies

Advances in lithography and thinner SiO/sub 2/ gate oxides have enabled the scaling of MOS technologies to sub-0.25-/spl mu/m feature size. High dielectric constant materials, such as Ta/sub 2/O/sub 5/, have been suggested as a substitute for SiO/sub 2/ as the gate material beyond t/sub ox//spl ap/25 /spl Aring/. However, the Si-Ta/sub 2/O/sub 5/ material system suffers from unacceptable levels of bulk fixed charge, high density of interface trap states, and low silicon interface carrier mobility. In this paper we present a solution to these issues through a novel synthesis of a thermally grown SiO/sub 2/(10 /spl Aring/)-Ta/sub 2/O/sub 5/ (MOCVD-50 /spl Aring/)-SiO/sub 2/ (LPCVD-5 /spl Aring/) stacked dielectric. Transistors fabricated using this stacked gate dielectric exhibit excellent subthreshold behaviour, saturation characteristics, and drive currents.

Scaling properties and short-channel effects in submicrometer AlGaAs/GaAs MODFET's: A Monte Carlo study

Scaling properties of n/sup +/-Al/sub x/Ga/sub 1-x/As/GaAs MODFETs with submicrometer gate lengths (L/sub G/=0.50 to 0.05 mu m) are examined, using Monte Carlo methods. High-frequency performance of MODFETs can be improved by scaling the gate lengths, but various studies suggest that there exists a lower limit for the gate after which no improvement should be expected. The lower limit is determined here to be approximately=0.10 mu m. Devices with smaller gate lengths than 0.1 mu m exhibit degraded transconductance (g/sub m/), large shift in threshold voltage due to poor charge control in the channel, and a sharp reduction in output resistance (R/sub o/). It is shown that the drain current saturation in MODFETs is not caused by the velocity saturation effect, but by channel pitch-off. Electron velocities calculated from Monte Carlo simulations and extracted from g/sub m/ and f/sub t/ measurements are reconciled. >

Improvement of hot carrier reliability with deuterium anneals for manufacturing multilevel metal/dielectric MOS systems

This paper discusses new experimental findings critical for process integration of deuterium post-metal anneals to improve channel hot carrier reliability in manufacturing multilevel metal CMOS integrated circuits. Detailed account of the deuterium process optimization experiments varying temperature, time, and ambient is given. Specifically, the first demonstration of the large hydrogen/deuterium isotope effect for multilevel metal/dielectric MOS systems is reported. Previous accounts of the isotope effect had been limited to CMOS structures with one-level of dielectric/metal and to about a 10 fold improvement in reliability. Deuterium, instead of hydrogen is introduced via an optimized post-metal anneal process to achieve a 50-100 fold improvement in transistor channel hot carrier lifetime. The benefits of the deuterium anneal are still observed even if the post-metal anneal is followed by the final SiN cap wafer passivation process. It is concluded that the deuterium post-metal anneal process is suitable for manufacturing high performance CMOS products and fully compatible with traditional integrated circuit processes.

Predictive worst case statistical modeling of 0.8- mu m BICMOS bipolar transistors: a methodology based on process and mixed device/circuit level simulators

The authors discuss the use of mixed-level physics-based device/circuit simulation software and semiconductor process simulator in the construction of predictive worst case process conditions for bipolar transistors currently being manufactured in AT&T 0.8- mu m BICMOS technology. Process fluctuations are introduced into the process simulator using the Latin hypercube (Monte Carlo) sampling method. The method is different from those in previous similar studies in that the compact device model parameter extraction step for each sample process is bypassed and active devices in the circuit are described by the physical device simulator rather than a compact model representation. This eliminates deficiencies associated with compact semiconductor device models. Furthermore, inaccuracies and difficulties introduced by compact model parameter extractions (especially for bipolar transistors) are also eliminated. The method is very useful in identifying critical process steps which determine the electrical performance of the devices and circuits. >

n/sup +/-polysilicon gate PMOSFET's with indium doped buried-channels

In this letter a n/sup +/-polysilicon gate PMOSFET with indium doped buried-channel is discussed, The gate length scaling of n/sup +/-polysilicon gate buried-length PMOSFETs is limited by the channel punch-through effect. Designing shallow counter-doped layers (buried-channels) has been established as a means to reduce the undesirable short channel effects in these devices. Indium, an acceptor dopant in Si, has a low diffusion coefficient and implant statistics favorable for achieving shallow doping layers. Indium implants are explored (as an alternative to BF/sub 2/) to counter dope the n-tub for adjusting the threshold voltage. Devices are fabricated using AT&Ts 0.5 /spl mu/m CMOS technology but with t/sub ox/=50 /spl Aring/. Although no special effort has been made to optimize the n-tub or to take full advantage of the diffusion and implant characteristics of indium, excellent electrical results are obtained for devices with L/sub eff/=0.25 /spl mu/m. Improved V/sub th/ roll-off characteristics and reduced body effect (/spl gamma//spl ap/0.18 V/sup 1/2 / versus /spl gamma//sub B//spl ap/0.40 V/sup 1/2 /) in indium implanted buried channels are demonstrated over BF/sub 2/ implanted buried channels for PMOSFETs with identical long channel threshold voltages. The effects of incomplete ionization (freeze-out) of the indium acceptor states on the electrical device characteristics are demonstrated by device simulations and measurements.

Degradation of gain in bipolar transistors

In this paper hot carrier related aging of n-p-n bipolar transistors is investigated experimentally and theoretically in order to bring physical insight into the bipolar h/sub FE/ (common emitter current gain) degradation. Electrical stress experiments are performed on transistors with different base doping profiles at varying temperatures. Detailed process simulations are performed to determine the doping profiles of the base-emitter junction. Monte Carlo transport simulations are then performed at different temperatures and bias conditions to determine the electron and hole distribution functions in the base-emitter junction. AT&Ts 0.8 /spl mu/m BICMOS technology is used to fabricate the experimental bipolar structures. For this non-self aligned technology we attribute h/sub FE/ degradation to the presence of hot holes and secondary electrons which are generated by hot hole impact ionization. This feedback due to impact ionization has a dominant effect on the high energy tails of the distribution of both holes and electrons even when the overall current multiplication is low. Simple hot electron energy transport models do not contain the complexity to properly describe ionization feedback and carrier heating, and are therefore inadequate. An exponential dependence of the transistor lifetime on BV/sub EBO/ is deduced for constant voltage stress (V/sub stress/ >

Monte Carlo study of GaAs/Al/sub x/ Ga/sub 1-x/As MODFETs: effects of Al/sub x/Ga/sub 1-x/As composition

Monte Carlo methods are used to compare electronic transport and device behavior in n/sup +/-Al/sub x/Ga/sub 1-x/As/GaAs modulation-doped field-effect transistors (MODFETs) at 300 K for x=0.10, 0.15, 0.22, 0.30, 0.35, and 0.40. The differences between the x=0.22 and x=0.30 MODFETs with respect to parasitic conduction in Al/sub x/Ga/sub 1-x/As, gate currents, and switching times, are of particular interest. The donor-related deep levels in Al/sub x/Ga/sub 1-x/As, are disregarded by assuming all donors to be fully ionized, and the focus is only on the confinement and transport of the carriers. The following quantities are studied in detail: transfer characteristics (I/sub D/ versus V/sub G/), transconductance (g/sub m/), switching speeds ( tau /sub ON/), parasitic conduction in Al/sub x/Ga/sub 1-x/As, gate current (I/sub G/), average electron velocities and energies in GaAs and Al/sub x/Ga/sub 1-x/As, electron concentration in the device domain, k-space transfer (to low mobility L and X valleys), and details of the real-space transfer process. >

Silicon npn bipolar transistors with indium-implanted base regions

In this paper, silicon npn bipolar transistors with indium-implanted base regions are discussed. Polysilicon emitter bipolar transistors are fabricated using a standard 0.5-/spl mu/m BIC-MOS process flow where the base BF/sub 2/ implant is replaced by an indium implant. In indium-implanted transistors, the integrated hole concentration (G/sub b/) in the quasi-neutral base is reduced due to incomplete ionization of indium acceptor states. The novel utilization of this impurity freeze-out effect results in much increased collector currents and common-emitter transistor gains (h/sub fe/) compared to boron-implanted transistors. Also, since indium acceptor states in depletion regions become fully ionized, the spreading of the reverse-biased collector-base junction depletion region into the transistor base (base-width modulation) is minimized. Hence, for indium base bipolar transistor an improved h/sub fe/-V/sub A/ product is anticipated. Our first attempt at fabricating bipolar transistors with indium-implanted base regions resulted in devices with greatly increased collector current, impressive gains of h/sub fe//spl ap/1600, excellent collector current saturation characteristics, an Early Voltage of V/sub A//spl ap/10 V, h/sub fe/-V/sub A/ product of 16000 (implying an extended device design space), base-emitter breakdown voltages of BV/sub EBO//spl ap/9.6 V, and a cut-off frequency of f/sub t/=17.8 GHz.

A very high performance and manufacturable 3.3 V 0.35-/spl mu/m CMOS technology for ASICs

In this paper a manufacturable and high performance 0.35 /spl mu/m CMOS ASIC technology optimized for 3.3 V operation is presented. This CMOS technology features a 65 /spl Aring/ gate oxide, single n/sup +/-polysilicon gate, and 3 levels of metal. An improvement of 1.6X in circuit performance and 1.56X in packing density is achieved over AT&Ts previous generation 0.5 /spl mu/m 3.3 volt CMOS technology by device scaling, and aggressive isolation and interconnect design rules. The nominal ring oscillator delay time is 50 ps.