Sundar Chetlur
Alcatel-Lucent
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Publication
Featured researches published by Sundar Chetlur.
Applied Physics Letters | 2002
Zhi Chen; Pangling Ong; Alicia Kay Mylin; Vijay P. Singh; Sundar Chetlur
Experiments based on substrate hot-electron generation due to impact ionization are designed to reveal whether the hydrogen/deuterium (H/D) isotope effect is caused by the density of electrons or their energy. It is found that the H/D isotope effect for hot-electron degradation is strongly dependent on the density of hot electrons presented at the interface. This suggests that the multiple vibrational excitation (heating) plays a major role in hot-carrier degradation of metal–oxide–semiconductor (MOS) transistors. Because of the unique nature of multiple vibrational excitation (heating), low-energy electrons are able to break Si–H/D bonds in MOS devices. This implies that hot-electron degradation is still an important reliability issue even if the drain voltage is scaled down to below 1 V.
Solid-state Electronics | 2000
Wei Li; J.S. Yuan; Sundar Chetlur; Jonathan Zhou; Anthony S. Oates
Abstract An improved substrate current model for deep submicron MOSFETs, suitable for circuit aging simulation, is developed. The present model predictions are compared with experimental data and the BSIM3V3 model. A good agreement between the present model predictions and experimental data is obtained.
international symposium on quality electronic design | 2001
Wei Li; Qiang Li; J.S. Yuan; Joshua McConkey; Yuan Chen; Sundar Chetlur; Jonathan Zhou; Anthony S. Oates
Because the supply voltage is not proportionally scaled with the device size, the further scaling down of CMOS devices is in turn accompanied with more and more severe hot-carrier reliability problems. Hot-carriers, the high energy carriers due to high electric field in the channel, are injected into the gate oxide or cause trapping states generation between Si and SiO/sub 2/ interface, which is accumulated and causes long run reliability problems in devices and circuits. In this paper, we describe a systematic method to evaluate the circuit degradation due to hot-carrier stressing. First the substrate current and gate leakage current models are improved for more accuracy in predicting the lifetime of the devices and circuits. The hot-carrier stressing characterization is carried out for 0.18 /spl mu/m technology. The circuit performance degradation is then evaluated using the parameters extracted from 0.18 /spl mu/m technology for both digital logic circuits and RF circuits.
IEEE Transactions on Electron Devices | 2001
Pradip Kumar Roy; Yuanning Chen; Sundar Chetlur
Graded gate oxide process involves a two-step synthesis of growing an oxide at a temperature above the viscoelastic temperature (T/sub VE/) onto a pregrown low temperature thermally grown SiO/sub 2/ layer to form a composite graded SiO/sub 2/ structure. The cooling rate is carefully modulated near T/sub VE//spl sim/925/spl deg/C to enhance growth induced stress relaxation. The pregrown SiO/sub 2/ layer provides grading and is a sink for stress accommodation for the final high temperature SiO/sub 2/ forming the interface. Both grading and modulated cooling generate a strain-free and planar Si/SiO/sub 2/ interface. Such an interface delivers significant enhancement in all aspects of device reliability and performance. These oxides are of very high-quality, robust, and manufacturable with a process capability index, C/sub pk/>1.5. Graded gate oxide is already in the primary path of our 0.16 /spl mu/m and 0.12 /spl mu/m technologies.
Applied Physics Letters | 2001
Zhi Chen; Pradeep Garg; Vijay P. Singh; Sundar Chetlur
An experiment that incorporates the deuterium isotope effect into the “hole trapping and electron filling” scenario in silicon metal–oxide–semiconductor (MOS) devices is presented. It is suggested that Lai’s physical model is only partially true in order to explain all of the observed MOS device degradation phenomena. The isotope effect is exclusively due to hot electrons, not hot holes. Holes might break the Si–O bonds to generate interface traps at VG near VT. The dominant degradation mechanism is the electron-stimulated Si–H bond breaking, although electron trapping also plays a role in degradation.
IEEE Transactions on Electron Devices | 2001
Zhi Chen; K. Y. Cheng; Jinju Lee; Joseph W. Lyding; K. Hess; Sundar Chetlur
Several new phenomena are observed comparing the AC stress with the DC stress. In the initial stress period ( 10/sup 4/ s), the saturation of the G/sub m/ degradation stops and the G/sub m/ degradation starts to increase again for AC stress, which is probably due to the hole trapping.
Photonics 2000: International Conference on Fiber Optics and Photonics | 2001
Pradip Kumar Roy; Yuan Chen; Sundar Chetlur
Graded-Grown-Gate oxide involves a 2-step synthesis of growing an oxide at a temperature above the viscoelastic temperature onto a pre-grown SiO2 layer. The cooling rate is carefully modulated near Tve-925 degrees C to enhance growth induced stress relaxation. This new ultra- thin gate oxide process is manufacturable and delivers significant improvement in transistor performance and exceptional reliability. These improvements are a consequence of a planar and stress-free Si/SiO2 generated by this novel process.
international integrated reliability workshop | 2000
Wei Li; J.S. Yuan; Sundar Chetlur; Jonathan Zhou; Anthony S. Oates
A simple and accurate substrate current model was developed by modifying the model of ionization characteristic length and tested for both n-channel and p-channel devices against the measurement data. It shows a better match by comparing with other models reported in the literature. The model has been used to simulate the transient substrate current in circuit operating conditions to show its ability to predict the device and circuit lifetime.
Microelectronic device technology. Conference | 1999
Sidhartha Sen; Edward Belden Harris; Richard William Gregor; Samuel Martin; Mahjoub A. Abdelgadir; Rafael N. Barba; Sundar Chetlur; Kurt Steiner
Experiments comparing High-Density Plasma (HDP) CVD oxide for gap-fill with a PECVD oxide/plasma etch process show effects on hot carrier reliability, transistor matching, and transistor 1/f noise. We present results from wafers processed in a 0.35 micrometers CMOS technology with three levels of metal. The results indicate that the HDP process used for gap-fill significantly improves matching and noise characteristics of metal covered devices. Both n and p channel current mirrors show improved matching between metal an no metal coverage with the HDP process. The presence of a HDP oxide film in IMD stack can reduce the mean threshold voltage difference between metal and no metal covered n- MOSFETs from 45 mV to about 4 mV. Likewise, the total integrated noise over the frequency range of 10 Hz-100 kHz of metal covered n-MOSFET is improved by a factor of 1.25 by the HDP gap-fill process. However, the HDP process has resulted in significant degradation of the d.c. hot carrier reliability of n-MOSFETs. These effects may be explained by the large amounts of hydrogen incorporated in the back-end dielectric with the HDP process.
Archive | 2001
Sundar Chetlur; Pradip Kumar Roy