Hemanth Jagannathan

Nature of germanium nanowire heteroepitaxy on silicon substrates

Systematic studies of the heteroepitaxial growth of germanium nanowires on silicon substrates were performed. These studies included the effect of sample preparation, substrate orientation, preanneal, growth temperature, and germane partial pressure on the growth of epitaxial germanium nanowires. Scanning electron microscopy and transmission electron microscopy were used to analyze the resulting nanowire growth. Germanium nanowires grew predominantly along the ⟨111⟩ crystallographic direction, with a minority of wires growing along the ⟨110⟩ direction, irrespective of the underlying silicon substrate orientation [silicon (111), (110), and (100)]. Decreasing the partial pressure of germane increased the number of ⟨111⟩ nanowires normal to the silicon (111) surface, compared to the other three available ⟨111⟩ directions. The growth rate of nanowires increased with the partial pressure of germane and to a lesser degree with temperature. The nucleation density of nanowire growth and the degree of epitaxy both...

Experimental study of biaxial and uniaxial strain effects on carrier mobility in bulk and ultrathin-body SOI MOSFETs

Biaxial and uniaxial strained silicon technologies are promising for enhancement of CMOS performance. However, the advantage of uniaxial/biaxial strain over biaxial/uniaxial strain in terms of carrier mobility is not clear, since biaxial and uniaxial strain effects on carrier mobility have not till date been directly compared. Furthermore, the carrier mobility under uniaxial strain has not been fully studied in terms of strain directions. On the other hand, in spite of the importance of ultrathin-body (UTB) SOI MOSFETs to suppress the short channel effects in sub-20-nm regime, strain effects in UTB MOSFETs with SOI thickness, T/sub SOI/, of less than 5nm have not be explored yet. In this report, biaxial and uniaxial strain effects on carrier mobility are systematically studied, for the fist time, utilizing externally applied mechanical stress. The biaxial and uniaxial strain effects in UTB MOSFETs with T/sub SOI/ of less than 5nm are also investigated, for the first time.

An Integrated Phase Change Memory Cell With Ge Nanowire Diode For Cross-Point Memory

We demonstrate a novel phase change memory cell utilizing doped Ge nanowire pn-junction diode both as a bottom electrode and a memory cell selection device. This memory cell can be used for a cross-point memory array with diode selection. Using selective growth of isolated vertical nanowires in each cell, we have minimized the contact area below the lithography limit. A very low SET programming current of 10s of muA was achieved. RESET/SET resistance ratio of 100x was obtained. The diode provides 100x isolation between forward and reverse bias in the SET state.

Engineering High Dielectric Constant Materials for Band-Edge CMOS Applications

This paper summarizes studies performed using capping layers in conjunction with high-K dielectrics to obtain band-edge CMOS devices. MgO and Al2O3 cap layers are evaluated for nFET and pFET devices respectively. By precisely positioning the cap materials in the gate stack and evaluating their effect as a function of process temperature and capping layer thickness, a deeper understanding of the mechanism of threshold voltage shift caused by the capping layers is obtained. MgO is observed to readily diffuse into the HfO2 stack at temperatures as low as 600 oC while Al2O3 diffuses through HfO2 at higher temperatures of 1000 oC. MgO caps located below the HfO2 and processed at 600 oC provide the best scaling and maximum voltage shift, while a trade-off between scaling and voltage shift has to be made when using Al2O3 caps.

Micro-fluidic channels with integrated ultrasonic transducers

This paper describes the work done in an attempt to integrate ultrasonic sensors in micro-fluidic channels. We have developed a system with fluidic channels having embedded zinc oxide transducers. A zinc oxide film is deposited on a glass substrate and is sandwiched between two electrodes. The transducers made are found to resonate at 400 MHz in thickness mode. The channels are made both from PDMS using a silicon master and from glass. These channels are aligned on top of the transducer forming a narrow path for fluid flow. The fluid of interest is pumped in the microchannels by means of a syringe pump and pulse echo measurements are done with the necessary circuitry. This paper will also show the results of the first experiments on mixing induced by the transducer and the measurement of physical dimensions, temperature of fluid in the channel using broad band pulse echo techniques.

Effect of oxide overlayer formation on the growth of gold catalyzed epitaxial silicon nanowires

A direct dependence between the inadvertent formation of SiO2 on gold films deposited on silicon ⟨111⟩ substrates, and the nucleation and yield of epitaxial, gold catalyzed, silicon nanowires grown on such substrates is reported. The unintended SiO2 layer formed due to the diffusion of silicon from the underlying substrate through the gold film is observed to be 0.5nm with medium energy ion scattering after brief exposures of 10–15min in air. Silicon nanowires grown at 500°C on such samples show reduced nucleation and growth. A remarkable improvement in nanowire nucleation density and epitaxy is observed on removing the SiO2 overlayer prior nanowire growth.

Broadband capacitive micromachined ultrasonic transducers ranging from 10 kHz to 60 MHz for imaging arrays and more

Capacitive micromachined ultrasonic transducers (CMUTs) have long been studied. Past research has shown that CMUTs indeed have remarkable features such as wide bandwidth and high efficiency. This paper introduces an inclusion to the CMUT technology that uses the wafer-bonding technique to fabricate membranes on silicon. This new technology enables the fabrication of large membranes with large gaps, and expands the frequency span of CMUTs to 10 kHz in the low end. CMUT devices with different frequency spans are fabricated using both technologies, and tested. Electromechanical coupling efficiency, k/sub T//sup 2/, value as high as 0.85 and fractional immersion bandwidth as wide as 175 % are measured.

Integrating Phase-Change Memory Cell With Ge Nanowire Diode for Crosspoint Memory—Experimental Demonstration and Analysis

In this paper, we demonstrate a novel phase-change memory cell utilizing a low-temperature in situ doped single crystalline germanium nanowire diode as a bottom electrode as well as a memory-cell selection device. The integrated memory cell shows promising characteristics such as low programming current, large set/reset resistance ratio, and rectifying behavior, which is required for high-density 3-D crosspoint memory. The small contact area determined by the diameter of nanowires enables low programming current below 200 for reset and 50 for set. The average resistance ratio of set/reset state programmed by repetitive pulse programming is 82, which is large enough for large-array operation. The heterojunction formed between in situ doped Ge nanowires and Si substrate provides isolation for crosspoint-memory operation.

High-K Gate Dielectric Structures by Atomic Layer Deposition for the 32nm and Beyond Nodes

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Templated germanium nanowire synthesis using oriented mesoporous organosilicate thin films

The authors report on a technique of combining low temperature nanowire synthesis with self-assembly of block copolymers in order to obtain a controlled array of nanowires. An oriented mesoporous inorganic thin film with ∼12nm pores was used as a template for synthesizing and controlling an array of vertical germanium nanowires. The number density of the nanowires growing through the pores was found to increase with an increase in the growth temperature. A low growth temperature of 275°C results in sparse nanowire growth while growth at 340°C results in approximately 50% of the pores being filled with nanowires. The growth through the pores is increased to close to 100% by growing the nanowires at a higher temperature of 380°C. Scanning electron micrographs confirm the presence of the nanowires conforming to the shape and dimensions of the pores. Transmission electron microscopy further reveals the microstructure of nanowires inside the pores to be polycrystalline. The technique of templated nanowire grow...