Vijay Narayanan

Advanced high-κ dielectric stacks with polySi and metal gates: recent progress and current challenges

The paper reviews our recent progress and current challenges in implementing advanced gate stacks composed of high-κ dielectric materials and metal gates in mainstream Si CMOS technology. In particular, we address stacks of doped polySi gate electrodes on ultrathin layers of high-κ dielectrics, dual-workfunction metal-gate technology, and fully silicided gates. Materials and device characterization, processing, and integration issues are discussed.

A Comparative Study of NBTI and PBTI (Charge Trapping) in SiO2/HfO2 Stacks with FUSI, TiN, Re Gates

Threshold voltage (V_t) of a field effect transistor (FET) is observed to shift with stressing time and this stress induced V _t shift is an important transistor reliability issue. V_t shifts that occur under negative gate bias is referred as NBTI and those that occur under positive bias is referred as PBTI or charge trapping. In this paper, we present a comparative study of NBTI and PBTI for a variety of FETs with different dielectric stacks and gate materials. The study has two parts. In part I, NBTI and PBTI measurements are performed for FUSI NiSi gated FETs with SiO₂ SiO₂/HfO₂ and SiO₂/HfSiO as gate dielectric stacks and the results are compared with those for conventional SiON/poly-Si FETs. The main results are: (i) NBTI for SiO ₂/NiSi and SiO₂/HfO₂/NiSi are same as those conventional SiON/poly-Si FETs; (ii) PBTI significantly increases as the Hf content in the high K layer is increased; and (iii) PBTI is a greater reliability issue than NBTI for HfO₂/NiSi FETs. In part II of the study, NBTI and PBTI measurements are performed for SiO2/HfO2 devices with TiN and Re as gates and the results are compared with those for NiSi gated FETs. The main results are: (i) NBTI for SiO ₂/HfO₂/TiN and SiO₂/HfO₂/Re pFETs are similar with those observed for NiSi gated pFETs; and (ii) PBTI in TiN and Re gated HfO₂ devices is much smaller than those observed for SiO₂/HfO₂/NiSi. In summary for SiO₂/HfO₂ stacks, NBTI is observed to be independent of gate material whereas PBTI is significantly worse for FUSI gated devices. Consequently, HfO₂ FETs with TiN and Re gates exhibit over all superior transistor reliability characteristics in comparison to HfO₂/FUSI FETs

A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications

Band-gap engineering using SiGe channels to reduce the threshold voltage (VTH) in p-channel MOSFETs has enabled a simplified gate-first high-к/metal gate (HKMG) CMOS integration flow. Integrating Silicon-Germanium channels (cSiGe) on silicon wafers for SOC applications has unique challenges like the oxidation rate differential with silicon, defectivity and interface state density in the unoptimized state, and concerns with Tinv scalability. In overcoming these challenges, we show that we can leverage the superior mobility, low threshold voltage and NBTI of cSiGe channels in high-performance (HP) and low power (LP) HKMG CMOS logic MOSFETs with multiple oxides utilizing dual channels for nFET and pFET.

A cost effective 32nm high-K/ metal gate CMOS technology for low power applications with single-metal/gate-first process

For the first time, we have demonstrated a 32 nm high-k/metal gate (HK-MG) low power CMOS platform technology with low standby leakage transistors and functional high-density SRAM with a cell size of 0.157 mum2. Record NMOS/PMOS drive currents of 1000/575 muA/mum, respectively, have been achieved at 1 nA/mum off-current and 1.1 V Vdd with a low cost process. With this high performance transistor, Vdd can be further scaled to 1.0 V for active power reduction. Through aggressive EOT scaling and band-edge work-function metal gate stacks, appropriate Vts and superior short channel control has been achieved for both NMOS and PMOS at Lgate = 30 nm. Compared to SiON-Poly, 30% RO delay reduction has been demonstrated with HK-MG devices. 40% Vt mismatch reduction has been shown with the Tinv scaling. Furthermore, it has been shown that the 1/f noise and transistor reliability exceed the technology requirements.

Band-Edge High-Performance High-k/Metal Gate n-MOSFETs Using Cap Layers Containing Group IIA and IIIB Elements with Gate-First Processing for 45 nm and Beyond

We have fabricated electrically reliable band-edge (BE) high-k/metal nMOSFETs stable to 1000degC, that exhibit the highest mobility (203 cm2/Vs @ 1MV/cm) at the thinnest Tinv (1.4 nm) reported to date. These stacks are formed by capping HfO2 with ultra-thin layers containing strongly electropositive gp. IIA and IIIB elements (e.g. Mg and La), prior to deposition of the TiN/Poly-Si electrode stack, in a conventional gate-first flow. Increasing the cap thickness tunes the Vt/V fb from a midgap position to BE while maintaining high mobility and good PBTI. The addition of La can enhance the effective k value of the dielectric stack, resulting in EOTs < 1nm. Short channel devices with band edge characteristics are demonstrated down to 60 nm. Finally, possible mechanisms to explain the nFET Vt shift are discussed

Examination of flatband and threshold voltage tuning of HfO2∕TiN field effect transistors by dielectric cap layers

The authors have examined the role of sub nanometer La2O3 and LaN cap layers interposed in Si∕HfO2∕TiN high-k gate dielectric stacks in tuning the flatband and threshold voltages of capacitors and transistors. High performance, band edge n metal oxide field effect transistors with channel lengths down to 60nm may be fabricated without significant compromise in mobility, electrical thickness, and threshold voltage. They have carried out a microstructural evaluation of these stacks and correlated these results with the electrical behavior of the devices.

High-performance high-κ/metal gates for 45nm CMOS and beyond with gate-first processing

Gate-first integration of band-edge (BE) high-κ/metal gate nFET devices with dual stress liners and silicon-on-insulator substrates for the 45nm node and beyond is presented. We show the first reported demonstration of improved short channel control with high-κ/metal gates (HK/MG) enabled by the thinnest Tinv (≪12Å) for BE nFET devices to-date, consistent with simulations showing the need for ≪14Å Tinv at Lgate≪35nm. We report the highest BE HK/MG nFET Idsat values at 1.0V operation. We also show for the first time BE high-κ/metal gate pFETs fabricated with gate-first high thermal budget processing with thin Tinv (≪13Å) and low Vts appropriate for pFET devices. The reliability in these devices was found to be consistent with technology requirements. Integration of high-κ/metal gate nFETs into CMOS devices yielded large SRAM arrays.

Epitaxial silicon and germanium on buried insulator heterostructures and devices

Future microelectronics will be based upon silicon or germanium-on-insulator technologies and will require an ultrathin (<10 nm), flat silicon or germanium device layer to reside upon an insulating oxide grown on a silicon wafer. The most convenient means of accomplishing this is by epitaxially growing the entire structure on a silicon substrate. This requires a high quality crystalline oxide and the ability to epitaxially grow two dimensional, single crystal films of silicon or germanium on top of this oxide. We describe a method based upon molecular beam epitaxy and solid-phase epitaxy to make such structures and demonstrate working field-effect transistors on germanium-on-insulator layers.

Understanding mobility mechanisms in extremely scaled HfO 2 (EOT 0.42 nm) using remote interfacial layer scavenging technique and V t -tuning dipoles with gate-first process

We demonstrate a novel “remote interfacial layer (IL) scavenging” technique yielding a record-setting equivalent oxide thickness (EOT) of 0.42 nm using a HfO2-based MOSFET high-к gate dielectric. Intrinsic effects of IL scaling on carrier mobility are clarified using this method. We reveal that the mobility degradation observed for La-containing high-к is not due to the La dipole but due to the intrinsic IL scaling effect, whereas an Al dipole brings about additional mobility degradation. This unique nature of the La dipole enables aggressive EOT scaling in conjunction with IL scaling for the 16 nm technology node without extrinsic mobility degradation.

Physical origins of mobility degradation in extremely scaled SiO2/HfO2 gate stacks with La and Al induced dipoles

We demonstrate metal-gate-induced interfacial layer (IL) scaling using a HfO2 dielectric and clarify the kinetics underlying this process. The intrinsic IL scaling effect on electron mobility is separated from La and Al-induced dipole effects. We find that the mobility degradation for La-containing high-κ dielectrics is not due to the La-induced dipole but due to the intrinsic IL scaling effect, whereas the Al-induced dipole brings about additional mobility degradation. This unique nature of the La-induced dipole enables aggressive equivalent oxide thickness scaling down to 0.42 nm without extrinsic mobility degradation when combined with IL scaling.