Hendra Kesuma

Hardware-accelerated reconstruction of compressed neural signals based on inpainting

In this paper the first low-latency architecture design and hardware implementation for structure-based inpainting to detect and complete isophotes in brain activity recording is presented. This novel mask-based compression and inpainting-based reconstruction methodology for correlated neural signals is especially important for the realization of implantable neural measurement systems (NMS) due to restrictions in terms of area and energy. The data compression is obtained by on/off controlling of the recording electrodes on implant side. The low-latency and parallel architecture design is based on a synchronous Moore-FSM for 16 bits inputs. It requires only 8 cycles to compute the inpainting-based detection and completion of isophotes. Because of the error-robust inpainting recovery procedure, small accuracy differences between the simulation and measurement results on a Xilinx DS312 Spartan-3E FPGA are negligible. The proposed hardware implementation on logical and physical 350nm CMOS reaches a clock frequency of 78.452 MHz, which leads to a throughput of 653 766 parallel inpainting-based isophote computations per second.

Low power ASIC design for infrared sensor network inside ARIANE 5 vehicle equipment bay

In this work the design of low power infrared transceiver ASIC with AMS350nm technology is presented. There are two different types of transceiver designs that have been developed. The first design is based on IrDA 9600 baud serial infrared (SIR) standard physical signal layer that uses split-phase Manchester coding technique and the second design is using uni-polar return zero coding (RZ) technique. The prototypes of the circuit are built and tested on a Field Programmable Gate Arrays (FPGA) Spartan-3E board provided by Digilent. After finishing the prototype, the ASIC synthesized, manufactured and tested. The infrared transceiver ASIC is intended for infrared sensor communication inside ARIANE launcher. Instead of using commercial infrared transceiver ICs, the ASIC design in this work is used as a blue print for radiation hardened ASIC design that can be qualified for the space environments. Other aspects such as Electromagnetic Compatibility (EMC) with launcher electrical equipment are also considered in the frame of the ASIC development.

Bit-Error-Rate measurement of infrared physical channel using reflection via Multi Layer Insulation inside in ARIANE 5 Vehicle Equipment Bay for wireless sensor network communication

In this work we investigate the Bit-Error-Rate (BER) of the Infrared (Ir) Communication inside the Vehicle Equipment Bay (VEB) of the ARIANE 5. Measurements were performed to find the impact of the reflection of the infrared signal via Multi Layer Insulation (MLI) on the infrared wireless sensor network (Ir WSN) communication in the VEB. The main focus is to find the relationship between the BER and the transmitting/receiving angle depending on variation of the Ir transmitter power. A further experiment was done by varying the transmission current with a constant angle for BER estimation without adding extra special signals (e.g. Additive white Gaussian noise (AWGN)) to the transmitter. Ambient white light from LEDs and 50 Hz fluorescent AC light was superimposed in the measurement to introduce additional noise for the infrared receiver into the physical channel.