Sebastian Schmale

Joint compression of neural action potentials and local field potentials

Brain research is concerned with two types of electrophysiological signals: neural action potentials (AP), which are also known as spikes, and local field potentials (LFP). The demand for an increased spatial and temporal resolution leads to an enlarged data rate which has to be handled by an assumed wireless link between the signal sources and the base station. Without data compression, these data rates would conflicting the neurophysiological restrictions in terms of low energy and low area consumption. The theory of Compressed Sensing (CS) can be utilized to perform data compression right after or during the acquisition of the neural data. In order to apply a joint CS infrastructure to AP and LFP, a common basis in which both signal types can be characterized as sufficiently sparse has to be found. In this paper, we investigate and compare four different well-known bases for the joint compression of LFP and AP of which the discrete cosine transform (DCT) turns out to be best suited.

Structure reconstruction of correlated neural signals based on inpainting for brain monitoring

This paper presents a novel approach for compressing neural signals. This topic is especially important for the realization of implantable neural measurement systems (NMS) since they are subject to strict constraints with regard to area and energy consumption. The handling of high data rate becomes a major topic within NMS. Compared to the often applied Compressed Sensing (CS) technique an approach steaming from image restoration is applied to NMS in this work for the first time: Inpainting strategies. The proposed Inpainting approach as well as CS focus on resource efficiency on transmitter (Tx) side in NMS. It can be shown, that the proposed approach outperforms CS in terms of recovery quality and thus is a promising alternative for the realization of innovative reliable NMS.

Compression and reconstruction methodology for neural signals based on patch ordering inpainting for brain monitoring

The aim of this study is to present the first compression and reconstruction methodology based on patch ordering inpainting algorithm for monitoring neural activity. This novel in-painting approach is especially important for the technical realization of implantable neural measurement systems (NMS) since they are subject to strict resource limitations as area and energy consumption. Intersection masks with center square as well as random-based masks are utilized for suitable neural data compression considering the patch ordering inpainting. The proposed inpainting methodology outperforms the structure-based inpainting algorithm and often applied Compressed Sensing strategy with regard to reconstruction quality of the real measured neural signals. These algorithms focus on complexity reduction according to hardware on implantable NMS. At high degrees of compression, the patch ordering inpainting yields well-suited or equal reconstruction results in contrast to JPEG or JPEG2000, respectively.

Rapid digital architecture design of orthogonal matching pursuit

Orthogonal Matching Pursuit (OMP) is a greedy algorithm well-known for its applications to Compressed Sensing. For this work it serves as a toy problem of a rapid digital design flow based on high-level synthesis (HLS). HLS facilitates extensive design space exploration in connection with a data type-agnostic programming methodology. Nonetheless, some algorithmic transformations are needed to obtain optimised digital architectures. OMP contains a least squares orthogonalisation step, yet its iterative selection strategy makes rank-1 updating possible. We furthermore propose to compute complex mathematical operations, e.g. the needed reciprocal square root operation, with the help of the logarithmic number system to optimise HLS results. Our results can compete with prior works in terms of latency and resource utilisation. Additionally and to the best of our knowledge, we can report on the first complex-valued digital architecture of OMP, which is able to recover a vector of length 128 with 5 non-zero elements in 17.1 μs.

High throughput architecture for inpainting-based recovery of correlated neural signals

This paper presents the first hardware architecture for compressing and reconstructing correlated neural signals using structure-based inpainting. This novel methodology is especially important for the realization of implantable neural measurement systems (NMS), which are subject to strict constraints in terms of area and energy consumption. Such an implant only requires a defined controlling of the electrode activity to compress neural data. To achieve an efficient implementation with high throughput at the data recovery, approximately computation of arithmetic operations and elementary functions is proposed by using the logarithmic number system (LNS). Because of the digital quantization effects of the LNS conversions, an inherent thresholding operation arises. The proposed hardware realization significantly reduces the required iteration of inpainting computations. This inherent zero forcing in conjunction with the algorithmic error correction results in a speed-up in terms of neural signal recovery, which results in a throughput of 32 961 parallel reconstructions per second.

Permuted cubes wavelet thresholding for mask-sensed MRI

In this work we present a novel inpainting algorithm to gain reduced acquisition time and high quality data reconstruction for MRI applications. We analyzed MRI recordings of two synthetically generated and of one real measured data set. On the basis of the proposed mask-based sampling trajectories, patients only have to spend a fraction of the recording time in the MRI. Especially, in the range of high k-space coefficient reduction, the reconstruction quality of our Permuted Cubes Wavelet Thresholding (PCWT) approach can compete with standard data compression-focused methods like JPEG2000 or MPEG-4. In all simulations, the proposed algorithm also outperforms state-of-the-art techniques such as BM3D-MRI with respect to accuracy after data reconstruction. Regarding the quality of the approximated MRI data, we mainly focus on the clear recovery of sharp edges without undesirable artifacts and the identification of tumors within MRI frames.

Efficient and fast SOP-based inpainting for neurological signals in resource limited systems

This work presents fast and efficient patch matching and ordering techniques for a novel inpainting-based compression and reconstruction methodology to continuously monitor neural activity. The mask-based compression is especially relevant for the technical realization of fully implantable neural measurement systems (NMS), because of restrictions regarding area and energy consumption. Novel approaches for decompression significantly reduce the number of computations for the procedure of smooth ordering patches (SOP) by a restricted neighboring search along consistent electrode patterns and by a patch group matching technique. Both combined yields a speed-up of 49.2x compared to an unrestricted patch search. With regard to recovered signal quality and compression of up to 95%, the proposed bridge mask achieves accurate results. The fast inpainting-based processing, including the proposed patch matching and ordering approaches, outperforms compression-focused standard techniques like JPEG and JPEG2000 regarding reconstruction quality of real measured neurological signals at high degrees of data reduction.

Hardware-accelerated reconstruction of compressed neural signals based on inpainting

In this paper the first low-latency architecture design and hardware implementation for structure-based inpainting to detect and complete isophotes in brain activity recording is presented. This novel mask-based compression and inpainting-based reconstruction methodology for correlated neural signals is especially important for the realization of implantable neural measurement systems (NMS) due to restrictions in terms of area and energy. The data compression is obtained by on/off controlling of the recording electrodes on implant side. The low-latency and parallel architecture design is based on a synchronous Moore-FSM for 16 bits inputs. It requires only 8 cycles to compute the inpainting-based detection and completion of isophotes. Because of the error-robust inpainting recovery procedure, small accuracy differences between the simulation and measurement results on a Xilinx DS312 Spartan-3E FPGA are negligible. The proposed hardware implementation on logical and physical 350nm CMOS reaches a clock frequency of 78.452 MHz, which leads to a throughput of 653 766 parallel inpainting-based isophote computations per second.

Fast digital design space exploration with high-level synthesis: A case study with approximate conjugate gradient pursuit

The rapid architecture design paradigm of highlevel synthesis (HLS) facilitates extensive design space exploration without much effort. Modern HLS compilers, like Xilinx Vivado HLS, support the evaluation of different architectures by so-called directives. We propose to extend the exploration capabilities through a data type-agnostic programming methodology. Automated by shell scripts, a link between the HLS tool and Mathworks Matlab facilitates the generation of large numbers of test vectors as stimuli to our designs for bit-accurate verification purposes. Additionally, we report on the first implementation of the Approximate Conjugate Gradient Pursuit algorithm, which is exemplarily used to demonstrate the augmented design space exploration capabilities.

Low power ASIC design for infrared sensor network inside ARIANE 5 vehicle equipment bay

In this work the design of low power infrared transceiver ASIC with AMS350nm technology is presented. There are two different types of transceiver designs that have been developed. The first design is based on IrDA 9600 baud serial infrared (SIR) standard physical signal layer that uses split-phase Manchester coding technique and the second design is using uni-polar return zero coding (RZ) technique. The prototypes of the circuit are built and tested on a Field Programmable Gate Arrays (FPGA) Spartan-3E board provided by Digilent. After finishing the prototype, the ASIC synthesized, manufactured and tested. The infrared transceiver ASIC is intended for infrared sensor communication inside ARIANE launcher. Instead of using commercial infrared transceiver ICs, the ASIC design in this work is used as a blue print for radiation hardened ASIC design that can be qualified for the space environments. Other aspects such as Electromagnetic Compatibility (EMC) with launcher electrical equipment are also considered in the frame of the ASIC development.