Jochen Rust

Low complexity QR-decomposition architecture using the logarithmic number system

In this paper we propose a QR-decomposition hardware implementation that processes complex calculations in the logarithmic number system. Thus, low complexity numeric format converters are installed, using nonuniform piecewise and multiplier-less function approximation. The proposed algorithm is simulated with several different configurations in a downlink precoding environment for 4×4 and 8×8 multi-antenna wireless communication systems. In addition, the results are compared to default CORDIC-based architectures. In a second step, HDL implementation as well as logical and physical CMOS synthesis are performed. The comparison to actual references highlight our approach as highly efficient in terms of hardware complexity and accuracy.

QR-decomposition architecture based on two-variable numeric function approximation

This paper presents a new approach for hardware-based QR-decomposition using an efficient computation scheme of the Givens-Rotation. In detail, the angle of rotation and its application to the Givens-Matrix are processed in a direct, straightforward manner. High-performance signal processing is achieved by piecewise approximation of the arctangent and sine function. In order to identify appropriate function approximations, several designs with varying constraints are automatically generated and analyzed. Physical and logical synthesis is performed in a 130 nm CMOS-technology. The application of our proposal in a multi-antenna mobile communication scenario highlights our work to be very efficient in terms of calculation accuracy and computation performance.

Design and implementation of a neurocomputing ASIP for environmental monitoring in WSN

In this paper the implementation of an application specific instruction set processor (ASIP) designed for online monitoring of perishable cargo freight is presented. It benefits flexible signal processing, considering actual environmental influences. As the use of artificial neural networks (ANN) has turned out to achieve convenient and efficient results, it is adapted to this application. Complex algebraic functions are realized by nonuniform linear piecewise function approximation as this increases computation effort and as a consequence energy-efficiency. Runtime evaluation is performed by comparison to actual references as well as the results of the physical synthesis are presented.

Design method for multiplier-less two-variable numeric function approximation

In this paper a novel method for hardware-based realization of two-variable numeric functions is introduced. The main idea is based on the extension of the well-known piecewise linear approximation technique, which is often used for the calculation of one-variable elementary functions. A nonuniform and plane segmentation scheme enables quick segment access at runtime; the use of multiplier-less linear equations causes high performance in terms of throughput. As both the extraction of approximation-related parameters and its mapping to corresponding hardware elements is automated, the design time is also reduced to a minimum. For evaluation, several approximations with varying constraints are generated and compared on the algorithmic level to one another as well as to actual references. In conjunction with the results of logical and physical CMOS synthesis, our work turns out to be highly efficient in terms of throughput, memory requirements and energy consumption.

A High Performance Neurocomputing Algorithm for Prediction Tasks in Wireless Sensor Networks

The impact of power efficient wireless sensor networks (WSN) is getting more and more important, as it is built of battery driven sensor nodes (SN). Beside common low power techniques like voltage scaling, variable-rate sampling (VRS) has been exposed as an adequate possibility to minimize the transceiver activity [1]. In this paper a high performance algorithm based on an artificial neural network structure (ANN) for WSN applications is presented which delivers adequate function course prediction, necessary for most precise sampling interval adjustment as described in [2]. Our approach is based on approximation by means of adjustment theory in detail linear regression [3] and algorithm adaption to the underlying low power TelosB SN hardware [4]. It is further implemented in the efficient fixed-point number format, and its experimental results are compared to common prediction algorithms.

Rapid digital architecture design of orthogonal matching pursuit

Orthogonal Matching Pursuit (OMP) is a greedy algorithm well-known for its applications to Compressed Sensing. For this work it serves as a toy problem of a rapid digital design flow based on high-level synthesis (HLS). HLS facilitates extensive design space exploration in connection with a data type-agnostic programming methodology. Nonetheless, some algorithmic transformations are needed to obtain optimised digital architectures. OMP contains a least squares orthogonalisation step, yet its iterative selection strategy makes rank-1 updating possible. We furthermore propose to compute complex mathematical operations, e.g. the needed reciprocal square root operation, with the help of the logarithmic number system to optimise HLS results. Our results can compete with prior works in terms of latency and resource utilisation. Additionally and to the best of our knowledge, we can report on the first complex-valued digital architecture of OMP, which is able to recover a vector of length 128 with 5 non-zero elements in 17.1 μs.

Two-variable numeric function approximation using least-squares-based regression

Automated design of two-variable numeric functions can be realized efficiently by extending well-known multiplier-less linear function approximation techniques; the arithmetic signal processing effort is minimized by the utilization of a non-uniform piecewise segmentation scheme. However, as common state-of-the-art approaches only consider unpretentious coefficient estimation techniques, such as gradient superposition, this results in large multiplexer-trees for segmentation that, consequently, are restricting the total performance. In this paper a least-squares-based estimation of multiplier-less linear coefficients is introduced that minimizes the number of segments by using a least-squares-based coefficient estimation. The evaluation indicates a reduction of the segmentation effort by nearly 31% on average. Logical and physical CMOS synthesis is performed and the results are compared to actual references highlighting our work high performance approach for the hardware-based calculation of two-variable numeric functions.

Reconfigurable architecture of a hybrid synchronisation algorithm for LTE

Time and frequency synchronisation are significant parts of the cell-search procedure and one of the first processing blocks within a mobile communication system. Particularly for an OFDM transmission within an initial synchronisation process, the algorithm has to deal with carrier frequency offsets up to several subcarrier spacings. To be able to still operate under those conditions, the cell-search procedure consists of different processing steps, combined in a hybrid algorithm. Beside good performance properties, hybrid algorithms lead to a high computational demand and implementation effort. To overcome these challenges, flexible architectures, which are able to select the most suitable algorithm during runtime, are the base for an efficient hardware realization. In this paper, as an example, we are introducing an hybrid initial synchronisation algorithm for an LTE-system, which still operates under the effect of a carrier frequency offset greater than the subcarrier spacing. Consecutively, we are showing a reconfigurable architecture as well as the results of an FPGA implementation of the time synchronisation part of that algorithm. The architecture is able to switch between different correlators, namely a reverse-auto, a cross- and a CP-based auto-correlation during runtime, which enables a flexible and low complexity realization of the computational complex synchronisation process.

Approximate computing of two-variable numeric functions using multiplier-less gradients

Abstract Approximate computing of non-trivial numeric functions is a well-known design technique and, therefore, used in several different application areas. Its main idea is the relaxation of conventional correctness constraints to achieve high performance results in terms of throughput and/or energy consumption. In this paper we propose an automated approximate design method for the fast hardware generation of two-dimensional numeric functions. By using multiplier-less gradients in combination with an advanced non-uniform segmentation scheme, high hardware performance is achieved. To qualify our approach, exhaustive evaluation is carried out, considering six different two-variable numeric functions. In a first step, a global complexity estimation is performed with varying design constraints on the algorithmic level. Out of this, most suitable candidates are selected for logic and physical CMOS synthesis. The results are compared to actual references highlighting our work as a powerful approach for the hardware-based calculation of two-variable numeric functions, especially in terms of throughput and energy consumption.

Hardware-Efficient QR-Decomposition Using Bivariate Numeric Function Approximation

Bivariate function approximation has proven its feasibility in terms of hardware-efficient arithmetic signal processing. However, its impact on high performance QR decomposition (QRD) has only been roughly studied so far. In this paper, a novel hardware architecture for Givens-Rotation-based QRD is proposed targeting hardware efficient signal processing. To this end, an ingenious triangular systolic array structure is considered. Complex-valued matrices are efficiently processed by means of a sophisticated bivariate numeric function approximation methodology. In order to get a comprehensive insight in the performance, exhaustive evaluation is carried out with a modern multi-antenna wireless communication system. In detail, the proposed QRD hardware architecture is used in a suitable channel pre-coding setup. For a meaningful proof-of-concept, our work is evaluated on several levels of the computing stack. In addition, our design is implemented and physically synthesized in a state-of-the-art 65-nm Taiwan Semiconductor Manufacturing Company technology and compared with other publications. The results indicate our approach to be a powerful solution for hardware-based QRD, especially in terms of energy and area requirements.