Heng Yuan Lee

Electrical evidence of unstable anodic interface in Ru∕HfOx∕TiN unipolar resistive memory

Unipolar resistive switching behaviors of Ru∕HfOx∕TiN devices with Ru as anode were investigated. Wide dispersion of switching operation parameters was observed. The conduction mechanisms in low and high resistance states of the devices were characterized to be Ohmic-like and tunneling, respectively. The band offset of the Ru∕HfOx interface was extracted from the measured tunneling current versus voltage characteristics. Instability of the band offset at the anodic interface was observed and may be responsible for the wide fluctuation of the operation voltage in the Ru∕HfOx∕TiN device at a high resistance state. The possible mechanism for these unstable characteristics of band offset at the Ru∕HfOx interface is also discussed.

Bipolar Resistive Memory With Robust Endurance Using AlCu as Buffer Electrode

A novel method of fabricating HfOx-based resistive memory device with excellent nonvolatile characteristics is proposed. By using a thin AlCu layer as the reactive buffer layer into the anodic side of a capacitor-like memory cell, excellent memory performances, which include reliable programming/erasing endurance (> 105 cycles), robust data retention at high temperature, and fast operation speed (< 50 ns), have been demonstrated. The resistive memory based on AlCu/HfOx stacked layer in this letter shows promising application in the next generation of nonvolatile memory.

AlOx-Based Resistive Switching Device with Gradual Resistance Modulation for Neuromorphic Device Application

AlOx-based resistive switching device (RRAM) with multi-level storage capability was investigated for the potential to serve as an electronic synapse device. The Ti/AlOx/TiN memory stack with memory size 0.48um×0.48um was fabricated; the resistive layer AlOx was deposited using atomic-layer- deposition (ALD) method. Multi-level resistance states were obtained by varying the compliance current levels or the applied voltage amplitudes during pulse cycling. These resistance states are thermally stable for over 1E5s at 125°C. The memory cell resistance can be continuously increased or decreased from each pulse cycle to pulse cycle. More than 1E5 endurance cycles and reading cycles were demonstrated. We further study the potential using this AlOx-based RRAM as electronic synapse device. Around 1% resistance change per pulse cycling was achieved and a plasticity learning rule pulse scheme was proposed to implement the memory device in large-scale hardware neuromorphic computing system.

Ferroelectricity of HfZrO 2 in Energy Landscape With Surface Potential Gain for Low-Power Steep-Slope Transistors

The corresponding energy landscape and surface potential are deduced from the experimental ferroelectricity of HfZrO2 (HZO) for low-power steep-slope transistor applications. The anti-ferroelectric (AFE) in annealed 600°C HZO extracted electrostatic potential gain from the measured polarization hysteresis loop and calculated subthreshold swing 33 mV/dec over six decades of IDS. A feasible concept of coupling the AFE HZO is experimentally established with the validity of negative capacitance and beneficial for steep-slope FET development in future generation.

Formation-Polarity-Dependent Improved Resistive Switching Memory Performance Using IrOx/GdOx/WOx/W Structure

The formation-polarity-dependent improved resistive switching memory performance using a new IrOx/GdOx/WOx/W structure has been investigated. The memory device has been observed by both high-resolution transmission electron microscopy and energy dispersive X-ray spectroscopy. The thicknesses of the GdOx and WOx layers are observed to be approximately 15 and 5.5 nm, respectively. All layers are also analyzed by X-ray photoelectron spectroscopy. The resistive switching mechanism is filament formation/rupture in the high-κ GdOx layer, which is controlled by the oxygen ion migration in bilayer GdOx/WOx films under negative and positive formation polarities. Excellent uniformity of SET/RESET voltages, low/high resistance states, and switching cycles have been observed under positive formation polarity owing to the charge trapping/detrapping in the high-κ GdOx switching layer. The memory device shows a long endurance of >104 times, and extrapolated 10-year data retention at 85 °C. This device shows great potential for future nonvolatile memory (NVM) applications.

Improvement of Uniformity of Resistive Switching Parameters by Selecting the Electroformation Polarity in IrOx/TaOx/WOx/W Structure

A route to improve the uniformity of key resistive switching memory parameters such as SET/RESET voltages, low/high-resistance states as well as switching cycles is demonstrated in an IrOx/TaOx/WOx/W simple resistive memory stack by selecting the electroformation polarity. The various stack layers are confirmed by high-resolution transmission electron microscopy, energy dispersive X-ray spectroscopy, and X-ray photoelectron spectroscopy analyses. Cumulative probability plots of the key memory parameters show tight distribution. The oxygen vacancy filaments are formed/ruptured owing to polarity-dependent oxygen ion migration, which is the switching mechanism in the TaOx/WOx bilayers, and improved resistive switching parameters under positive formation polarity are observed. The fabricated device has shown good potential for multilevel capability with a low voltage operation of ±3 V. The device has shown an excellent read endurance of >105 cycles and data retention up to 10 years at 85 °C.

HfOx Bipolar Resistive Memory With Robust Endurance Using AlCu as Buffer Electrode

A novel method of fabricating HfOx-based resistive memory device with excellent nonvolatile characteristics is proposed. By using a thin AlCu layer as the reactive buffer layer into the anodic side of a capacitor-like memory cell, excellent memory performances, which include reliable programming/erasing endurance (> 105 cycles), robust data retention at high temperature, and fast operation speed (< 50 ns), have been demonstrated. The resistive memory based on AlCu/HfOx stacked layer in this letter shows promising application in the next generation of nonvolatile memory.

Simulation-based study of negative-capacitance double-gate tunnel field-effect transistor with ferroelectric gate stack

The concept of ferroelectric (FE) negative capacitance (NC) may be a turning point in overcoming the physical limitations imposed by the Boltzmann tyranny to realize next-generation state-of-the-art devices. Both the body factor (m-factor) and the transport mechanism (n-factor) are simultaneously improved by integrating an NC with a tunnel FET (TFET). The modeling approach is discussed in this study as well as the NC physics. By optimizing the thicknesses of FE, semiconductor, and interfacial layers, the capacitance of the FE layers is modulated to match that of a MOS resulting in the smallest subthreshold swing that is also hysteresis-free. An ultrathin-body double gate tunnel FET (UTB-DG-TFET) exhibits a steep slope (a subthreshold swing below 10 mV/dec over more than 4 orders of magnitude) for low-power applications (<0.2 V switching voltage) to realize next-generation state-of-the-art devices.

Impact of self-complementary resistance switch induced by over-reset energy on the memory reliability of hafnium oxide based resistive random access memory

The degradation behavior of the Ti/HfOx bipolar resistive random access memory (RRAM) during endurance cycles, and the operational parameters, which induce the endurance failure, are studied through the two proposed stressing methods. The over-RESET energy is considered to be the key electrical parameter to induce endurance failure in the memory device. When the device suffers the over-RESET energy, a gradually reduced memory window is observed associated with endurance cycles, and the overall degradation will include two stages. The first stage can be explained by the worn filament model and is mainly due to imbalance energy between SET and RESET process. The occurrence of unusual resistance–voltage (R–V) patterns at positive and negative voltage seep in the memory device under the second stage degradation demonstrates the existence of complementary resistive switching (CRS) in the single Ti/HfOx bipolar RRAM. After analyzing the operation conditions to activate the self-CRS in memory device with one transistor–one resistor (1T–1R) configuration, the mechanism about the second stage degradation in the RRAM originated from over-RESET energy is also discussed. A mechanism based on the worn filament model and the induction of CRS is proposed to explain the endurance failure induced by over-RESET in the Ti/HfOx RRAM with 1T–1R configuration. With an appropriate RESET energy, a robust reliability for endurance cycles is expected.

Circuit design challenges and trends in read sensing schemes for resistive-type emerging nonvolatile memory

Nonvolatile memory has become a bottleneck in attempts to reduce the energy consumption of electronic systems. Several emerging forms of nonvolatile memory have shown promise in overcoming these difficulties, achieving faster write speeds and lower power operations than those afforded by Flash memories. Unfortunately, constraints related to bitline bias-voltage, small read cell current, and process variation detract considerably from the efficiency of read operations. This paper provides a review of the challenges and trends associated with the read sensing circuitry used in emerging nonvolatile memories.