Imad ud Din

A receiver for LTE Rel-11 and beyond supporting non-contiguous carrier aggregation

Carrier aggregation (CA) is introduced in 3GPP LTE Rel-10 [1] to meet the demand for further increased bitrates. While LTE Rel-10 supports simultaneous reception of two carriers either in contiguous intra-band or in inter-band CA configuration, the upcoming LTE Rel-11 will add support for non-contiguous (NC) carriers within bands. Supporting NC CA in handsets is a demanding challenge for several reasons. Foremost, the total bandwidth spanned by the carriers may be several times the bandwidth of the individual carriers, possibly spanning an entire band with interfering signals between desired carriers. Furthermore, the distance between TX and RX carriers will vary and worse, may be much smaller than the fixed duplex distance for LTE Rel-8 and W-CDMA single carrier operation [2-5].

Wideband SAW-Less Receiver Front-End With Harmonic Rejection Mixer in 65-nm CMOS

A wideband direct-conversion receiver front-end featuring a new harmonic rejection technique is demonstrated in 65-nm CMOS. The circuit consists of a two-stage low-noise amplifier, the first stage with capacitive feedback, a harmonic rejection mixer using 25% and 50% duty cycle local oscillator signals, and a third-order channel-select filter with configurable bandwidth. The receiver front-end is intended for surface-acoustic-wave-less cellular applications, and its performance was measured at 900- and 1800-MHz bands. The average harmonic rejection over GSM and LTE channel bandwidths is between 60 and 70 dB. Peak harmonic rejection exceeds 80 dB. The noise figures (NFs) are 3.3 and 3.9 dB for the complete receiver front-end in low band and high band, respectively, with an S11 below -15 dB from 500 MHz to 2.5 GHz. The 1-dB received signal compression points with a blocker present at 20/80 MHz offset for low/high band are 0 and +2 dBm, respectively. The NF with 0-dBm blocker is 13 dB. For low band, the in-band IIP3 and IIP2 are -14.8 and > 49 dBm, respectively, and, for high band, -18.2 and > 44 dBm. The circuit worst case consumes 80 mW of power.

Complex IF Harmonic Rejection Mixer for Non-Contiguous Dual Carrier Reception in 65 nm CMOS

This paper presents a complex IF mixer for a double conversion receiver architecture to be used for non-contiguous dual carrier reception as specified in upcoming releases of 3GPP standards. The complex IF mixer contains four harmonic rejection (HR) mixers, each of which is implemented with 64 passive unit cell mixers, clocked by a ring-oscillator based phase-locked loop and driven by sequencers that represent thermometer-coded oversampled sinusoidal LO waveforms. Each HR mixer is followed by a buffer and a signal distribution network to enable separation of the two carriers as well as IQ-imbalance correction. The complex IF mixer supports reception of two carriers with up to 65 MHz separation using 12 samples per IF LO period and a clock frequency of 390 MHz. The IF mixer is implemented in 65 nm CMOS, has an area of 0.74 mm2, draws 26 mA, and has a harmonic conversion lower than -68 dBc per harmonic.

A 4.75–34.75 MHz digitally tunable active-RC LPF for >60dB mean RX IRR in 65nm CMOS

A third order active-RC Chebyshev low-pass filter for a mobile terminal receiver supporting carrier aggregation is presented. It has a 0.4 dB passband ripple, reconfigurable bandwidth (4.75-34.75 MHz), automatic RC tuning, and IQ-mismatch correction. The noise power spectral density referred to the filter input is 3.8pA/√Hz at 90 % of the bandwidth. The output referred third order intercept point (OIP3) is 39.4 dBm for a two tone input at 47 MHz and 70 MHz. By digitally controlling the passive circuit elements of the filter, the frequency dependent gain and phase IQ mismatch can be reduced, resulting in a remaining gain error below 0.35 % and a maximum phase error of 0.23 degrees. After calibration, the IQ matching is sufficient for a mean receiver image-rejection ratio of more than 60 dB. The current consumption is 39 mA from a 1.2 V supply.

A 1.5 V 28 GHz Beam Steering SiGe PLL for an 81-86 GHz E-Band Transmitter

This letter presents measurement results for a low supply voltage 28 GHz beam steering PLL, designed in a SiGe bipolar process with fT = 200 GHz. The PLL, designed around a QVCO, is intended for a beam steering 81-86 GHz E-band transmitter. Linear phase control is implemented by variable current injection into a Gilbert type phase detector, with a measured nominal phase control sensitivity of 2.5 °/μA. The demonstrated LO generation method offers great advantages in the implementation of beam steering mm-wave transmitters, since only the low frequency PLL reference signal of 1.75 GHz needs to be routed across the chip to the different transmitters. Except for an active loop filter, used to extend the locking range of the PLL, the design uses a low supply voltage of 1.5 V. The PLL obtains a measured in band phase noise of -107 dBc/Hz at 1 MHz offset. The power consumption equals 54 mW from the 1.5 V supply plus 1.8 mW for the variable supply of the active low pass filter.

Complex IF harmonic rejection mixer for non-contiguous dual carrier reception in 65 nm CMOS

This paper presents a complex IF mixer for a double conversion receiver architecture to be used for non-contiguous dual carrier reception as specified in upcoming releases of 3GPP standards. The complex IF mixer contains four harmonic rejection (HR) mixers, each of which is implemented with 64 passive unit cell mixers individually driven by a sequencer to represent an oversampled sinusoidal LO waveform. Each HR mixer is followed by a buffer and a signal distribution network to enable separation of the two carriers as well as IQ-imbalance calibration. The complex IF mixer supports reception of two carriers with up to 65 MHz separation with 12 samples per IF LO period and a clock frequency of 390 MHz. The IF mixer is implemented in 65 nm CMOS, has an area of 0.48 mm2, draws 19.7 mA, and has a harmonic conversion lower than -68 dBc per harmonic.

A 28 GHz SiGe QVCO and divider for an 81–86 GHz E-band beam steering transmitter PLL

This paper presents a QVCO and divider for a 28 GHz SiGe PLL. It was designed in a SiGe process with fT= 200 GHz. The PLL is intended to be used for beam steering in an 81-86 GHz E-band transmitter. Phase control is implemented by programmable current injection into the loop filter. The simulations in Spectre use a layout extracted view with parasitics for the QVCO and the frequency divider and an ADS Momentum model for the QVCO inductors. The divider is implemented with four cascaded current-mode-logic (CML) blocks, for a reference frequency of 1.75 GHz. The low frequency parts of the PLL were represented with either Verilog-A or schematic models. The phase noise of the QVCO equals -105 dBc/Hz at 1MHz offset, while at the same offset the divider standalone has an input referred phase noise of -110 dBc/Hz. The phase control has been verified by transient simulations showing a phase control sensitivity of 1.5°/μA over a range exceeding 360°. With a supply of 1.5 V the QVCO and divider consumes 29 mA.

Wideband Reconfigurable Capacitive shunt-feedback LNA in 65nm CMOS

A differential LNA using capacitive shunt feedback is demonstrated in 65nm CMOS. The capacitive shunt feedback structure gives a wideband input matching, S11 <;-17 dB from 500MHz - 1 GHz for low band and S11 <;-20 dB from 1.1 GHz - 2.3GHz for high band. The NF for the complete receiver chain in low band and high band was measured to 3.3 dB and 3.9 dB, respectively. The 1-dB compression point with a 0dBm blocker present at 20MHz offset is 0dBm and the NFdsb with 0dBm blocker is 13 dB. In-band IIP3, and IIP2 are -14.8 dBm, and >;49 dBm, respectively for low band and -18.2dBm and >;44dBm for high band.

Highly linear direct conversion receiver using customized on-chip balun

This paper presents a highly linear radio frequency receiver front-end with on-chip balun for cellular application at 2GHz in 65nm CMOS technology. Based on direct conversion architecture, the implemented front-end comprises a customized on-chip balun for single-ended to differential signal conversion, a differential common-gate low noise amplifier and voltage mode quadrature passive mixer. The simulated in-band compression point is −0.5dBm and third order input intercept point is +6.2dBm. An out-of-band blocker compression point up to +4.8dBm and third order input intercept point of +16dBm are achieved thanks to the frequency translation filtering technique. The low-noise amplifier consumes 3mA current using 1.8V supply. The overall noise figure including balun loss, low-noise amplifier, mixer and a simplified model of a baseband filter is 3.8dB.

Two Tunable Frequency Duplexer Architectures for Cellular Transceivers

In this paper, two architectures for tunable duplexers are presented. The tuning is accomplished through variable capacitance and resistance. The architectures are based on a three element series-parallel resonator, with one pass and one stop frequency. Both architectures rely on filtering as well as cancellation for good Tx to Rx isolation while maintaining low insertion loss. The first architecture, the filtered transformer balanced (FTB) isolator, has single ended transmit and antenna ports and a differential receive port. The second architecture, the cross coupled filtering (CCF) isolator, is fully differential. For a resonator