Johan Wernehag

Wideband SAW-Less Receiver Front-End With Harmonic Rejection Mixer in 65-nm CMOS

A wideband direct-conversion receiver front-end featuring a new harmonic rejection technique is demonstrated in 65-nm CMOS. The circuit consists of a two-stage low-noise amplifier, the first stage with capacitive feedback, a harmonic rejection mixer using 25% and 50% duty cycle local oscillator signals, and a third-order channel-select filter with configurable bandwidth. The receiver front-end is intended for surface-acoustic-wave-less cellular applications, and its performance was measured at 900- and 1800-MHz bands. The average harmonic rejection over GSM and LTE channel bandwidths is between 60 and 70 dB. Peak harmonic rejection exceeds 80 dB. The noise figures (NFs) are 3.3 and 3.9 dB for the complete receiver front-end in low band and high band, respectively, with an S11 below -15 dB from 500 MHz to 2.5 GHz. The 1-dB received signal compression points with a blocker present at 20/80 MHz offset for low/high band are 0 and +2 dBm, respectively. The NF with 0-dBm blocker is 13 dB. For low band, the in-band IIP3 and IIP2 are -14.8 and > 49 dBm, respectively, and, for high band, -18.2 and > 44 dBm. The circuit worst case consumes 80 mW of power.

A 24-GHz Automotive Radar Transmitter with Digital Beam Steering in 130-nm CMOS

In this paper simulations of a 130-nm CMOS 24-GHz automotive radar transmitter with digital beam steering is presented. The beam steering is performed by multiple PAs connected to separate antenna elements. The output phases of the PAs are individually controllable through 360deg by binary weighting of quadrature phases. The circuit contains 18 PAs, each delivering 0 dBm to the antenna, resulting in a combined output power of 13 dBm. The 18 element antenna array will at 24 GHz be 11 cm, and have a directivity of 12 dB and a half power beam width of 5 degrees

A 1.5 V 28 GHz Beam Steering SiGe PLL for an 81-86 GHz E-Band Transmitter

This letter presents measurement results for a low supply voltage 28 GHz beam steering PLL, designed in a SiGe bipolar process with fT = 200 GHz. The PLL, designed around a QVCO, is intended for a beam steering 81-86 GHz E-band transmitter. Linear phase control is implemented by variable current injection into a Gilbert type phase detector, with a measured nominal phase control sensitivity of 2.5 °/μA. The demonstrated LO generation method offers great advantages in the implementation of beam steering mm-wave transmitters, since only the low frequency PLL reference signal of 1.75 GHz needs to be routed across the chip to the different transmitters. Except for an active loop filter, used to extend the locking range of the PLL, the design uses a low supply voltage of 1.5 V. The PLL obtains a measured in band phase noise of -107 dBc/Hz at 1 MHz offset. The power consumption equals 54 mW from the 1.5 V supply plus 1.8 mW for the variable supply of the active low pass filter.

A 0.25W fully integrated class-D audio power amplifier in 0.35μm CMOS

A fully integrated class-D audio power amplifier using Pulse Width Modulation (PWM) technique is presented. The output stage is an H-bridge with 5.75 mm wide nMOS transistors and 15 mm wide pMOS transistors, which can deliver up to 0.25 Wrms to an 16 Omega load. The chip measuring 1.2times2.4 mm2, including pads, was fabricated in a 0.35 mum CMOS process. It uses a single 3.3 V supply and a PWM carrier frequency of 2.5 MHz. The chip was designed and simulated with Cadence IC design tools as a student project in the course IC- project and verification at Lund University. The chip was verified and works well with a measured THD+N of 0.5% and efficiency of 76% at 0.25 Wrms output power into 16 Omega.

Teaching top down design of analog/mixed signal ICs through design projects

This paper describes a project course that focuses on the design of analog and mixed signal circuits through a systematic top down design flow. In the project, the student will be involved in the planning, modeling, circuit level design, physical level implementation and measurement verification of for example a successive approximation (SA) ADC or a class-D audio amplifier. Throughout the project, the project members will improve their design skills and create an understanding for the importance of a systematic top-down design methodology at the different levels of the design flow.

An 8-GHz Beamforming Transmitter IC in 130-nm CMOS

An 8-GHz beamforming transmitter IC has been designed in a 130-nm CMOS process. Two power amplifiers with independently controllable phase enable the beamforming. The phases are digitally controllable over the full 360deg range, which is accomplished by binary weighting of quadrature phase signals in the power amplifiers. The quadrature phase signals are generated by a quadrature voltage controlled oscillator followed by a buffer, which serves as an isolation between the power amplifiers and the oscillator. The chip contains seven on-chip differential inductors, and consumes a total of 47 mA from a 1.0 V supply. The measured output power is -3 dBm for each power amplifier.

Comparison of two SiGe 2-stage E-band power amplifier architectures

This paper presents simulation and measurement results for two 2-stage E-band power amplifiers implemented in 0.18 μm SiGe technology with fr = 200 GHz. To increase the power gain by mitigating the effect of the base-collector capacitance, the first design uses a differential cascode topology with a 2.7 V supply voltage. The second design instead uses capacitive cross-coupling of a differential common emitter stage, previously not demonstrated in mm-wave SiGe PAs, and has a supply voltage of only 1.5 V. Low supply voltage is advantageous since a common supply can then be shared between the transceiver and the PA. To maximize the power gain and robustness, both designs use a transformer based interstage matching. The cascode design achieves a measured power gain, S21, of 16 dB at 92 GHz with 17 GHz 3-dB bandwidth, and a simulated saturated output power, Psat, of 17 dBm with a 16% peak PAE. The cross-coupled design achieves a measured S21 of 10 dB at 93 GHz with 16 GHz 3-dB bandwidth, and a simulated Psat, of 15 dBm with 16% peak PAE. Comparing the measured and simulated results for the two amplifier architectures, the cascode topology is more robust, while the cross-coupled topology would benefit from a programmable cross-coupling capacitance.

A 28 GHz SiGe QVCO and divider for an 81–86 GHz E-band beam steering transmitter PLL

This paper presents a QVCO and divider for a 28 GHz SiGe PLL. It was designed in a SiGe process with fT= 200 GHz. The PLL is intended to be used for beam steering in an 81-86 GHz E-band transmitter. Phase control is implemented by programmable current injection into the loop filter. The simulations in Spectre use a layout extracted view with parasitics for the QVCO and the frequency divider and an ADS Momentum model for the QVCO inductors. The divider is implemented with four cascaded current-mode-logic (CML) blocks, for a reference frequency of 1.75 GHz. The low frequency parts of the PLL were represented with either Verilog-A or schematic models. The phase noise of the QVCO equals -105 dBc/Hz at 1MHz offset, while at the same offset the divider standalone has an input referred phase noise of -110 dBc/Hz. The phase control has been verified by transient simulations showing a phase control sensitivity of 1.5°/μA over a range exceeding 360°. With a supply of 1.5 V the QVCO and divider consumes 29 mA.

Wideband Reconfigurable Capacitive shunt-feedback LNA in 65nm CMOS

A differential LNA using capacitive shunt feedback is demonstrated in 65nm CMOS. The capacitive shunt feedback structure gives a wideband input matching, S11 <;-17 dB from 500MHz - 1 GHz for low band and S11 <;-20 dB from 1.1 GHz - 2.3GHz for high band. The NF for the complete receiver chain in low band and high band was measured to 3.3 dB and 3.9 dB, respectively. The 1-dB compression point with a 0dBm blocker present at 20MHz offset is 0dBm and the NFdsb with 0dBm blocker is 13 dB. In-band IIP3, and IIP2 are -14.8 dBm, and >;49 dBm, respectively for low band and -18.2dBm and >;44dBm for high band.

Highly linear direct conversion receiver using customized on-chip balun

This paper presents a highly linear radio frequency receiver front-end with on-chip balun for cellular application at 2GHz in 65nm CMOS technology. Based on direct conversion architecture, the implemented front-end comprises a customized on-chip balun for single-ended to differential signal conversion, a differential common-gate low noise amplifier and voltage mode quadrature passive mixer. The simulated in-band compression point is −0.5dBm and third order input intercept point is +6.2dBm. An out-of-band blocker compression point up to +4.8dBm and third order input intercept point of +16dBm are achieved thanks to the frequency translation filtering technique. The low-noise amplifier consumes 3mA current using 1.8V supply. The overall noise figure including balun loss, low-noise amplifier, mixer and a simplified model of a baseband filter is 3.8dB.