Herve Levi

Improvement of aging simulation of electronic circuits using behavioral modeling

This paper presents an original method of analog circuits aging simulation. This method is based on a behavioral modelling of circuits that includes the effects of degradations on circuit parameters, on the basis of transistors aging. The efficiency of the method is demonstrated in the case of hot carriers degradation in an amplifier

A VHDL-AMS library of RF blocks models

This paper presents a behavioral model library of analogue and mixed circuits used in the radio-frequency domain. The models are described in VHDL-AMS and are carefully documented and validated, in order to be easily used by designers or model developers. These models allow one to explore systems architecture easily and rapidly.

Study and behavioural simulation of phase noise and jitter in oscillators

This paper investigates the phase noise and the jitter in oscillators. We have simulated in the transient domain the jitter of a voltage controlled oscillator (VCO) using an AHDL model. Simulation results verify the basic theory of oscillator jitter. The developed model can be adapted for any oscillator circuit and used to determine the effect of VCO jitter on a larger system such as a frequency synthesiser.

Electrical aging behavioral modeling for reliability analyses of ionizing dose effects on an n-MOS simple current mirror.

Nowadays, a deterministic approach based on physics of failure is necessary to estimate the lifetime of integrated circuits. Therefore, the reliability analyses via electrical/aging simulations are performed during the design phase. Our previous works consisted in generating an aging behavioral model of a circuit in order to assess its degradation level and to predict its lifetime according to its mission profile. This paper presents obtained experimental results using our developed methodology to evaluate the influence of total ionizing dose effects on an n-MOS simple current mirror taking into account technological dispersions.

VHDL-AMS modelling and Optimization of a Fractional-N Synthesizer with experiment Designs

In this work, we expose our approach to design and optimize mixed analogue and digital systems at a high level description using the hardware description language VHDL-AMS. Many statistical experimental design methods are employed in optimization. We apply Hocke_D4 experimental designs with five parameters in order to minimize the lock time and the spurious level of a fractional-N synthesizer acting as a direct MSK modulator and designed for the DECT standard application.

High level optimization of a MSK modulator with experience plans - application to DECT standard

In this work, we expose our approach to design and optimize mixed analog and digital systems at a high level description using VHDL-AMS. The studied system consists of a MSK modulator designed and optimized for a DECT standard application. The applied optimization method uses the “experience plans” with five generics having in view to minimize the modulator response time. At this level, we can talk about virtual prototyping making possible the characterization of a designed system and the prediction of its performances before developing a transistor level description.

Fast and accurate behavioural simulation of fractional-N frequency synthesizer for the optimization of the lock time

Today, the current need consisting of implementing more and more complex systems imply the implementation of new methodologies to make the CAD product reliable in order to improve time to market, study costs, reusability and reliability of the design process. This paper proposes a high level design approach applied for the simulation and the optimization of fractional-N synthesizer acting as a direct GPSK modulator and designed for the UMTS standard application. It uses the hardware description language VHDL-AMS and a genetic algorithm to optimize the modulator with a considerably reduced CPU time.

High level characterization and optimization of a GPSK modulator with genetic algorithm

Today, design requirements are extending more and more from electronic (analogue and digital) to multidiscipline ones. These current needs imply implementation of methodologies to make the CAD product reliable in order to improve time to market, study costs, reusability and reliability of the design process. This paper proposes a high level design approach applied for the characterization and the optimization of fractional-N synthesizer acting as a direct GPSK modulator and designed for the UMTS standard application. It uses the hardware description language VHDL-AMS and a genetic algorithm to optimize the modulator with a considerably reduced CPU time before passing to a transistor level characterization.

Improvement of ageing simulation of electronic circuits based on behavioural modelling

In this paper, we will demonstrate how to improve the ageing simulation by the use of a behavioural modelling language like VHDL-AMS, in order to efficiently simulate the reliability of integrated circuit in their electrical context.

Hierarchical analogue design and behavioural modelling

This paper describes a new project oriented course which has been set-up recently at the University of Bordeaux, France, in co-operation with the institute of Microelectronics Bordeaux IXL. This course, held within the curriculum of the microelectronics engineer education, introduces the concept of hierarchical design of analogue circuits and analogue HDL like VerilogA or VHDL-AMS circuit modelling to the students. It is composed of a short lecture part and a major laboratory part where well-known design software is used. A phase-locked-loop (PLL), defined in the literature, has been taken as a design example to be investigated by the students. The scope of this course is to familiarise the behavioural modelling approach during the design phase of analogue circuits.