Hesameddin Ilatikhameneh

Efficient and realistic device modeling from atomic detail to the nanoscale

As semiconductor devices scale to new dimensions, the materials and designs become more dependent on atomic details. NEMO5 is a nanoelectronics modeling package designed for comprehending the critical multi-scale, multi-physics phenomena through efficient computational approaches and quantitatively modeling new generations of nanoelectronic devices as well as predicting novel device architectures and phenomena. This article seeks to provide updates on the current status of the tool and new functionality, including advances in quantum transport simulations and with materials such as metals, topological insulators, and piezoelectrics.

Tunnel Field-Effect Transistors in 2-D Transition Metal Dichalcogenide Materials

In this paper, the performance of tunnel field-effect transistors (TFETs) based on 2-D transition metal dichalcogenide (TMD) materials is investigated by atomistic quantum transport simulations. One of the major challenges of TFETs is their low ON-currents. 2-D material-based TFETs can have tight gate control and high electric fields at the tunnel junction, and can, in principle, generate high ON-currents along with a subthreshold swing (SS) smaller than 60 mV/decade. Our simulations reveal that high-performance TMD TFETs not only require good gate control, but also rely on the choice of the right channel material with optimum bandgap, effective mass, and source/drain doping level. Unlike previous works, a full-band atomistic tight-binding method is used self-consistently with 3-D Poisson equation to simulate ballistic quantum transport in these devices. The effect of the choice of the TMD material on the performance of the device and its transfer characteristics are discussed. Moreover, the criteria for high ON-currents are explained with a simple analytic model, showing the related fundamental factors. Finally, the SS and energy delay of these TFETs are compared with conventional CMOS devices.

Electrically Tunable Bandgaps in Bilayer MoS2

Artificial semiconductors with manufactured band structures have opened up many new applications in the field of optoelectronics. The emerging two-dimensional (2D) semiconductor materials, transition metal dichalcogenides (TMDs), cover a large range of bandgaps and have shown potential in high performance device applications. Interestingly, the ultrathin body and anisotropic material properties of the layered TMDs allow a wide range modification of their band structures by electric field, which is obviously desirable for many nanoelectronic and nanophotonic applications. Here, we demonstrate a continuous bandgap tuning in bilayer MoS2 using a dual-gated field-effect transistor (FET) and photoluminescence (PL) spectroscopy. Density functional theory (DFT) is employed to calculate the field dependent band structures, attributing the widely tunable bandgap to an interlayer direct bandgap transition. This unique electric field controlled spontaneous bandgap modulation approaching the limit of semiconductor-to-metal transition can open up a new field of not yet existing applications.

Polarization-Engineered III-Nitride Heterojunction Tunnel Field-Effect Transistors

The concept and simulated device characteristics of tunneling field-effect transistors (TFETs) based on III-nitride heterojunctions are presented for the first time. Through polarization engineering, interband tunneling can become significant in III-nitride heterojunctions, leading to the potential for a viable TFET technology. Two prototype device designs, inline and sidewall-gated TFETs, are discussed. Polarization-assisted p-type doping is used in the source region to mitigate the effect of the deep Mg acceptor level in p-type GaN. Simulations indicate that TFETs based on III-nitride heterojunctions can be expected to achieve ON/OFF ratios of 106 or more, with switching slopes well below 60 mV/decade, ON-current densities approaching 100 μA/μm, and energy delay products as low as 67 aJ-ps/μm.

Dielectric Engineered Tunnel Field-Effect Transistor

The dielectric engineered tunnel field-effect transistor (DE-TFET) as a high-performance steep transistor is proposed. In this device, a combination of high-k and low-k dielectrics results in a high electric field at the tunnel junction. As a result, a record ON-current of ~1000 μA/μm and a subthreshold swing (SS) below 20 mV/decade are predicted for WTe2 DE-TFET. The proposed TFET works based on a homojunction channel and electrically doped contacts both of which are immune to interface states, dopant fluctuations, and dopant states in the bandgap, which typically deteriorate the OFF-state performance and SS in the conventional TFETs.

Few-layer Phosphorene: An Ideal 2D Material For Tunnel Transistors

2D transition metal dichalcogenides (TMDs) have attracted a lot of attention recently for energy-efficient tunneling-field-effect transistor (TFET) applications due to their excellent gate control resulting from their atomically thin dimensions. However, most TMDs have bandgaps (Eg) and effective masses (m*) outside the optimum range needed for high performance. It is shown here that the newly discovered 2D material, few-layer phosphorene, has several properties ideally suited for TFET applications: 1) direct Eg in the optimum range ~1.0–0.4 eV, 2) light transport m* (0.15 m0), 3) anisotropic m* which increases the density of states near the band edges, and 4) a high mobility. These properties combine to provide phosphorene TFET outstanding ION ~ 1 mA/um, ON/OFF ratio ~ 106 for a 15 nm channel and 0.5 V supply voltage, thereby significantly outperforming the best TMD-TFETs and CMOS in many aspects such as ON/OFF current ratio and energy-delay products. Furthermore, phosphorene TFETS can scale down to 6 nm channel length and 0.2 V supply voltage within acceptable range in deterioration of the performance metrics. Full-band atomistic quantum transport simulations establish phosphorene TFETs as serious candidates for energy-efficient and scalable replacements of MOSFETs.

Design Guidelines for Sub-12 nm Nanowire MOSFETs

Traditional thinking assumes that a light effective mass (m*), high mobility material will result in better transistor characteristics. However, sub-12-nm metal-oxide-semiconductor field effect transistors (MOSFETs) with light m* may underperform compared to standard Si, as a result of source to drain (S/D) tunneling. An optimum heavier mass can decrease tunneling leakage current, and at the same time, improve gate to channel capacitance because of an increased quantum capacitance (Cq). A single band effective mass model has been used to provide the performance trends independent of material, orientation and strain. This paper provides guidelines for achieving optimum m* for sub-12-nm nanowire down to channel length of 3 nm. Optimum m* are found to range between 0.2-1.0 m0 and more interestingly, these masses can be engineered within Si for both p-type and n-type MOSFETs. m* is no longer a material constant, but a geometry and strain dependent property of the channel material.

Can Homojunction Tunnel FETs Scale Below 10 nm

The main promise of tunnel FETs (TFETs) is to enable supply voltage (VDD) scaling in conjunction with dimension scaling of transistors to reduce power consumption. However, reducing VDD and channel length (Lch) typically deteriorates the ONand OFF-state performance of TFETs, respectively. Accordingly, there is not yet any report of a high performance TFET with both low VDD (∼0.2V) and small Lch (∼6nm). In this work, it is shown that scaling TFETs in general requires scaling down the bandgap Eg and scaling up the effective mass m∗ for high performance. Quantitatively, a channel material with an optimized bandgap (Eg ∼ 1.2qVDD[eV ]) and an engineered effective mass (m∗−1 ∼ 40V 2.5 DD[m 0 ]) makes both VDD and Lch scaling feasible with the scaling rule of Lch/VDD = 30 nm/V for Lch from 15nm to 6nm and corresponding VDD from 0.5V to 0.2V.The main promise of tunnel FETs (TFETs) is to enable supply voltage (V_DD) scaling in conjunction with dimension scaling of transistors to reduce power consumption. However, reducing V_DD and channel length (L_ch) typically deteriorates the ON- and OFF-state performance of TFETs, respectively. Accordingly, there is not yet any report of a high-performance TFET with both low V_DD (~0.2 V) and small L_ch (~6 nm). In this letter, it is shown that scaling TFETs in general requires scaling down the bandgap Eg and scaling up the effective mass m* for high performance. Quantitatively, a channel material with an optimized bandgap (E_g ~ 1.2qV_DD [eV]) and an engineered effective mass (m*^-1 ~ 40V_DD^2.5 [m₀^-1 ]) makes both V_DD and L_ch scaling feasible with the scaling rule of L_ch/V_DD = 30 nm/V for L_ch from 15 to 6 nm and the corresponding V_DD from 0.5 to 0.2 V.

Configurable Electrostatically Doped High Performance Bilayer Graphene Tunnel FET

A bilayer graphene-based electrostatically doped tunnel field-effect transistor (BED-TFET) is proposed. Unlike graphene nanoribbon TFETs in which the edge states deteriorate the OFF-state performance, BED-TFETs operate based on bandgaps induced by vertical electric fields in the source, channel, and drain regions without any chemical doping. The performance of the transistor is evaluated by self-consistent quantum transport simulations. This device has several advantages: 1) ultra-low power (VDD=0.1 V); 2) high performance (ION/IOFF >104); 3) steep subthreshold swing (SS<;10mv/dec); and 4) electrically configurable between N-TFET and P-TFET post fabrication. The operation principle of the BED-TFET and its performance sensitivity to the device design parameters are presented.

Direct Observation of 2D Electrostatics and Ohmic Contacts in Template-Grown Graphene/WS2 Heterostructures

Large-area two-dimensional (2D) heterojunctions are promising building blocks of 2D circuits. Understanding their intriguing electrostatics is pivotal but largely hindered by the lack of direct observations. Here graphene-WS2 heterojunctions are prepared over large areas using a seedless ambient-pressure chemical vapor deposition technique. Kelvin probe force microscopy, photoluminescence spectroscopy, and scanning tunneling microscopy characterize the doping in graphene-WS2 heterojunctions as-grown on sapphire and transferred to SiO2 with and without thermal annealing. Both p-n and n-n junctions are observed, and a flat-band condition (zero Schottky barrier height) is found for lightly n-doped WS2, promising low-resistance ohmic contacts. This indicates a more favorable band alignment for graphene-WS2 than has been predicted, likely explaining the low barriers observed in transport experiments on similar heterojunctions. Electrostatic modeling demonstrates that the large depletion width of the graphene-WS2 junction reflects the electrostatics of the one-dimensional junction between two-dimensional materials.