Michael Povolotskyi

NEMO5: A Parallel Multiscale Nanoelectronics Modeling Tool

The development of a new nanoelectronics modeling tool, NEMO5, is reported. The tool computes strain, phonon spectra, electronic band structure, charge density, charge current, and other properties of nanoelectronic devices. The modular layout enables a mix and match of physical models with different length scales and varying numerical complexity. NEMO5 features multilevel parallelization and is based on open-source packages. Its versatility is demonstrated with selected application examples: a multimillion-atom strain calculation, bulk electron and phonon band structures, a 1-D Schrödinger-Poisson simulation, a multiphysics simulation of a resonant tunneling diode, and quantum transport through a nanowire transistor.

Efficient and realistic device modeling from atomic detail to the nanoscale

As semiconductor devices scale to new dimensions, the materials and designs become more dependent on atomic details. NEMO5 is a nanoelectronics modeling package designed for comprehending the critical multi-scale, multi-physics phenomena through efficient computational approaches and quantitatively modeling new generations of nanoelectronic devices as well as predicting novel device architectures and phenomena. This article seeks to provide updates on the current status of the tool and new functionality, including advances in quantum transport simulations and with materials such as metals, topological insulators, and piezoelectrics.

Engineering Nanowire n-MOSFETs at L-g < 8 nm

As metal-oxide-semiconductor field-effect transistors (MOSFETs) channel lengths (Lg) are scaled to lengths shorter than Lg <; 8 nm source-drain tunneling starts to become a major performance limiting factor. In this scenario, a heavier transport mass can be used to limit source-drain (S-D) tunneling. Taking InAs and Si as examples, it is shown that different heavier transport masses can be engineered using strain and crystal-orientation engineering. Full-band extended device atomistic quantum transport simulations are performed for nanowire MOSFETs at Lg <; 8 nm in both ballistic and incoherent scattering regimes. In conclusion, a heavier transport mass can indeed be advantageous in improving ON-state currents in ultrascaled nanowire MOSFETs.

Engineering Nanowire n-MOSFETs at

As metal-oxide-semiconductor field-effect transistors (MOSFETs) channel lengths (Lg) are scaled to lengths shorter than Lg <; 8 nm source-drain tunneling starts to become a major performance limiting factor. In this scenario, a heavier transport mass can be used to limit source-drain (S-D) tunneling. Taking InAs and Si as examples, it is shown that different heavier transport masses can be engineered using strain and crystal-orientation engineering. Full-band extended device atomistic quantum transport simulations are performed for nanowire MOSFETs at Lg <; 8 nm in both ballistic and incoherent scattering regimes. In conclusion, a heavier transport mass can indeed be advantageous in improving ON-state currents in ultrascaled nanowire MOSFETs.

L_{g}

Empirical tight binding(ETB) methods are widely used in atomistic device simulations. Traditional ways of generating the ETB parameters rely on direct fitting to bulk experiments or theoretical electronic bands. However, ETB calculations based on existing parameters lead to unphysical results in ultra small structures like the As terminated GaAs ultra thin bodies(UTBs). In this work, it is shown that more reliable parameterizations can be obtained by a process of mapping ab-initio bands and wave functions to tight binding models. This process enables the calibration of not only the ETB energy bands but also the ETB wave functions with corresponding ab-initio calculations. Based on the mapping process, ETB model of Si and GaAs are parameterized with respect to hybrid functional calculations. Highly localized ETB basis functions are obtained. Both the ETB energy bands and wave functions with subatomic resolution of UTBs show good agreement with the corresponding hybrid functional calculations. The ETB methods can then be used to explain realistically extended devices in non-equilibrium that can not be tackled with ab-initio methods.

Tight-binding analysis of Si and GaAs ultrathin bodies with subatomic wave-function resolution

Thermal properties are of great interest in modern electronic devices and nanostructures. Calculating these properties is straightforward when the device is made from a pure material, but problems arise when alloys are used. Specifically, only approximate band structures can be computed for random alloys and most often the virtual crystal approximation (VCA) is used. Unfolding methods [Boykin, Kharche, Klimeck, and Korkusinski, J. Phys.: Condens. Matter 19, 036203 (2007)] have proven very useful for tight-binding calculations of alloy electronic structure without the problems in the VCA, and the mathematical analogy between tight-binding and valence-force-field approaches to the phonon problem suggests they be employed here as well. However, there are some differences in the physics of the two problems requiring modifications to the electronic-structure approach. We therefore derive a phonon alloy band-structure (vibrational-mode) approach based on our tight-binding electronic-structure method, modifying the band-determination method to accommodate the different physical situation. Using the method, we study

Brillouin zone unfolding method for effective phonon spectra

\mathrm{In}(x)\mathrm{Ga}(1\ensuremath{-}x)\mathrm{As}

Simulation Study of Thin-Body Ballistic n-MOSFETs Involving Transport in Mixed

alloys and find very good agreement with available experiments.

\Gamma

Transistor designs based on using mixed Γ-L valleys for electron transport are proposed to overcome the density of states bottleneck while maintaining high injection velocities. Using a self-consistent top-of-the-barrier transport model, improved current density over Si is demonstrated in GaAs/AlAsSb, GaSb/AlAsSb, and Ge-on-insulator-based single-gate thin-body n-channel metal-oxide-semiconductor field-effect transistors. All the proposed designs successively begin to outperform strained-Si-on-insulator and InAs-on-insulator (InAs-OI) in terms of ON-state currents as the effective oxide thickness is reduced below 0.7 nm. InAs-OI still exhibits the lowest intrinsic delay (τ) due to its single Γ valley.

-L Valleys

It is critical to capture the effect due to strain and material interface for device level transistor modeling. We introduce a transferable