Heung-Soo Im

High-performance 1-Gb-NAND flash memory with 0.12-/spl mu/m technology

A 1.8-V, 1-Gb NAND flash memory is fabricated with 0.12-/spl mu/m CMOS STI process technology. For higher integration, a 32-cell NAND structure, which enables row decoder layout in one block pitch, is applied for the first time. Resulting cell and die sizes are 0.076 /spl mu/m/sup 2/ and 129.6 mm/sup 2/, respectively. A pseudo-4-phase charge pump circuit can generate up to 20 V even under the supply voltage of 1.6 V. A newly applied cache program function and expanded page size of (2 k + 64) byte lead to program throughput of 7 MB/s. The page copy-back function is provided for on-chip garbage collection. The read throughput of 27 MB/s is achieved by simply expanding I/O width and page size. A measured disturbance free-window of 3.5 V at 1.5 V-V/sub DD/ is obtained.

Highly manufacturable 1 Gb NAND flash using 0.12 /spl mu/m process technology

An 1 Gb NAND flash memory has been successfully developed by integrating new technologies, inverse narrow-width effect (INWE) suppression scheme, 32-cell NAND flash combined with the scaling-down of tunnel oxide, inter-poly ONO, and gate poly re-oxidation. It is implemented using KrF photolithography along with a resolution enhancing technique, the planarized surface by etch-back and CMP processes, highly selective contact etching and nonoverlapped dual damascene metallization. Thus, for the first time, a 1 Gb NAND flash memory with mass-producible chip size of 132 mm/sup 2/, lower Vcc operation below 1.8 V and lower power consumption, has been obtained.

A 1.8 V 1 Gb NAND flash memory with 0.12 /spl mu/m STI process technology

A 1.8 V 1 Gb flash memory uses a 0.12 /spl mu/m STI process technology. A charge pump operates at <1.8 V. A center-placed row decoder is digitized in one block pitch by applying a 32-cell NAND structure. A page buffer, containing two latches, supports a cache-program to improve program speed to 7 MB/s.

A 3.3 V 133 MHz 32 Mb synchronous mask ROM [in CMOS]

A 32Mb synchronous mask ROM (SMROM) improves performance of systems using mask ROM (MROM). SMROM has multiplexed address pins as does synchronous DRAM (SDRAM) to reduce the number of address pins. Since pin functions and commands of SMROM are almost identical to those of SDRAM, SMROM can share the same SDRAM bus and can be controlled by the SDRAM controller with minor modification. The device operates either in single-word (SW) mode for 16b data bus, or in double-word (DW) mode for 32b data bus, by use of a WORD control pin.