Hideaki Kuroda

High Performance 65nm SOI Transistors Using Laser Spike Annealing

In this paper we present enhancements in transistor performance and manufacturability of a high performance 65nm node SOI transistor by the combination of reduced RTA temperature and laser spike anneal (LTRTA+LSA) achieved through simultaneous optimization of offset spacer and extension/halo. DC NFET drive current is increased by 10% to a value of 1120 muA/mum (1220muA/mum if 9% NFET SOI self-heating effect included) at 200nA/mum off-state current and VDD of 1.0V. PMOS drive current is enhanced by 5% to a value of 575muA/mum (60OmuA/mum if 5% PFET SOI self-heating effect included) which is less than enhancement observed in the NFET due to the differing amount of enhancement of capacitive inversion thickness (TINV) at short channel. With respect to circuit and product performance, this device provides a 5% delay improvement for a product-like ring-oscillator (RO) and results in an improved cross-die statistical distribution of RO delay time. The minimum stable SRAM operating voltage (Vmin) is also significantly improved, indicating that control of the overlap capacitance (Cov) may play a significant role in determining SRAM Vmin. For the first time, we report that the NFET Tinv reduction by LSA is substantially larger at shorter channel lengths which explains the large NFET drive current enhancements obtained by LSA

A Study of Transient Thermal Spreading of VLSI Packaging With Multi Level Scaling

Trend of VLSI chip power consumption sounds switch over from the Moore’s law to more moderate curve by the “multi core processing” paradigm. Many of the recent advanced VLSI chips adopt the multiple processing units since clock enhancement is no longer feasible to gain the expected performance based on realistic range of power consumption. Even though, heat flux may keep increasing by further fine semiconductor process and may keep localizing by further complex logics. In this study, thermal impact of hot spot size relative to chip size or the dimension of heat sink is investigated by analytic modeling as well as numerical analysis. The analytic transient thermal spreading model in a solid with transfer function has already proposed and was validated in our previous work. In this study, we have considered the impact of thermal interface between the heat source and conductive and spreading component to the sink. Thermal response in wide rage of scales is discussed from transistor level to a millimeter scale. Each level of such various sizes can be investigated individually and can be built up with some sort of cascade manner. Based on this model, thermal diffusion in silicon substrate, which has the thermal coupling with spreader and thermal interface, will be discussed for a further fine process generation of the chip. The result implies that passive thermal spreading can be achieving to the limit.Copyright