John G. Pellerin

High-performance nMOSFET with in-situ phosphorus-doped embedded Si:C (ISPD eSi:C) source-drain stressor

For the first time, embedded Si:C (eSi:C) was demonstrated to be a superior nMOSFET stressor compared to SMT or tensile liner (TL) stressors. eSi:C nMOSFET showed higher channel mobility and drive current over our best poly-gate 45 nm-node nMOSFET with SMT and tensile liner stressors. In addition, eSi:C showed better scalability than SMT plus tensile liner stressors from 380 nm to 190 nm poly-pitches.

A 45 nm CMOS node Cu/Low-k/ Ultra Low-k PECVD SiCOH (k=2.4) BEOL Technology

A high performance 45nm BEOL technology with proven reliability is presented. This BEOL has a hierarchical architecture with up to 10 wiring levels with 5 in PECVD SiCOH (k=3.0), and 3 in a newly-developed advanced PECVD ultralow-k (ULK) porous SiCOH (k=2.4). Led by extensive circuit performance estimates, the detrimental impact of scaling on BEOL parasitics was overcome by strategic introduction of ULK at 2times wiring levels, and increased 1times wire aspect ratios in low-k, both done without compromising reliability. This design point maximizes system performance without adding significant risk, cost or complexity. The new ULK SiCOH film offers superior integration performance and mechanical properties at the expected k-value. The dual damascene scheme (non-poisoning, homogeneous ILD, no trench etch-stop or CMP polish-stop layers) was extended from prior generations for all wiring levels. Reliability of the 45 nm-scaled Cu wiring in both low-k and ULK levels are proven to meet the criteria of prior generations. Fundamental solutions are implemented which enable successful ULK chip-package interaction (CPI) reliability, including in the most aggressive organic flip-chip FCPBGA packages. This represents the first successful implementation of Cu/ULK BEOL to meet technology reliability qualification criteria

A low-temperature metal-doping technique for engineering the gate electrode of replacement metal gate CMOS transistors

This work describes a low-temperature metal annealing technique that can be a helpful tool for fabricating the gate electrode of replacement metal gate CMOS transistors. The goal of the technique is to form doped metal (TaSiN, TiSiN, TaCN, TaPN, etc.) to change the work function of the metal gate electrode. The low-temperature doping process was performed in an ambient containing the precursors of the dopants, including silane, phosphine, and carbon-rich organic precursors. Experiments have been conducted to incorporate dopants such as P, C, Si into TaN or TiN. The transistor and C-V data show the resultant doped metals are suitable materials for P- and N-MOSFETs by providing the right metal work function.

Low Dielectric Constant Fluorinated Polyimides for Interlayer Dielectric Applications

This paper presents the results of development, characterization and integration screening of low dielectric constant (low k) fluorinated polyimides for interlayer dielectric applications. Evolution of these materials has progressed with the intent of improving fundamental thin film properties, such as thermal stress behavior, modulus, CTE, and dielectric constant. Further refinements to fluorinated polyimides have been to improve their process compatibility and integration characteristics, primarily in the area of deep sub-micron gap filling. The avenues taken to attain these objectives will be illustrated. Subsequent integration of low k fluorinated polyimides has been achieved for a completed single-level metal BEOL test vehicle to highlight the impacts of the films adhesion, mechanical and thermomechanical properties. In addition, the completed fluorinated polyimide single-level metal structures have been used to characterize electrical performance in contrast to single-level metal structures with TEOS dielectric. Intralevel capacitance and leakage current have been measured with dual comb and serpentine structures. Modeling has been applied to verify dielectric constant in submicron geometries from the capacitance measurements.

High Performance 65nm SOI Transistors Using Laser Spike Annealing

In this paper we present enhancements in transistor performance and manufacturability of a high performance 65nm node SOI transistor by the combination of reduced RTA temperature and laser spike anneal (LTRTA+LSA) achieved through simultaneous optimization of offset spacer and extension/halo. DC NFET drive current is increased by 10% to a value of 1120 muA/mum (1220muA/mum if 9% NFET SOI self-heating effect included) at 200nA/mum off-state current and VDD of 1.0V. PMOS drive current is enhanced by 5% to a value of 575muA/mum (60OmuA/mum if 5% PFET SOI self-heating effect included) which is less than enhancement observed in the NFET due to the differing amount of enhancement of capacitive inversion thickness (TINV) at short channel. With respect to circuit and product performance, this device provides a 5% delay improvement for a product-like ring-oscillator (RO) and results in an improved cross-die statistical distribution of RO delay time. The minimum stable SRAM operating voltage (Vmin) is also significantly improved, indicating that control of the overlap capacitance (Cov) may play a significant role in determining SRAM Vmin. For the first time, we report that the NFET Tinv reduction by LSA is substantially larger at shorter channel lengths which explains the large NFET drive current enhancements obtained by LSA

Implementation of Robust Nickel Alloy Salicide Process for High-Performance 65nm SOI CMOS Manufacturing

Addition of Pt to Ni silicide produces a robust [NixPt(1-x)]Si, which shows an improved morphological stability, an important reduction in encroachment defect density, a reduced tendency to form NiSi2 and significant variations in monosilicide texture without degrading the device performance or the yield of high-performance 65 nm SOI technologies.

Self-aligned nickel, cobalt/tantalum nitride stacked-gate pMOSFETs fabricated with a low temperature process after metal electrode deposition

This letter reports the first replacement (Damascene) metal gate pMOSFETs fabricated with Ni/TaN, Co/TaN stacked electrode, where Ni or Co is in direct contact with the gate SiO/sub 2/, to adjust the electrode metal work function and TaN is used as the filling material for the gate electrode to avoid wet etching and CMP problems. The process is similar to the fabrication of traditional self-aligned polysilicon gate MOSFETs, except that in the back end (after the source/drain implants are activated) a few processing steps are added to replace the polysilicon with metal. Our data show that the Ni or Co/TaN gate electrode has the right work function for the pMOSFETs. The metal gate process can reduce the gate resistivity. Thermal stability of the stacked electrodes is studied and the result is reported in this paper. The damascene process flow bypasses high temperature steps (> 400/spl deg/C)critical for metal gate and hi k materials. This paper demonstrates that a low temperature anneal (300/spl deg/C) can improve the device performance. In this paper, the gate dielectrics is SiO/sub 2/.

CVD rhenium and PVD tantalum gate MOSFETs fabricated with a replacement technique

This letter reports the first replacement metal gate MOSFETs with chemical vapor deposition (CVD) Rhenium (Re), and physical vapor deposition (PVD) Tantalum (Ta) as the stacked gate electrode. Transistors with PVD Ta electrode are fabricated with a replacement and a nonself-aligned method for comparison. Our data show that CVD Re can be implemented as a gate electrode material for MOS transistors. The CVD Re process has the advantage of reducing the plasma and radiation damages to the gate oxide. A thick layer of PVD Ta covering a thin layer of CVD Re forms the stacked gate structure and makes the metal chemical-mechanical polishing feasible.

Integrated Circuits & Manufacturing - Advanced CMOS Logic and SoC Platforms

The development of CMOS platforms in this session focuses on the manufacturing readiness and continued advancements within the 45nm technology generation and the emergence of 32nm logic technology development efforts. After a long anticipated introduction, we see high-k / metal gate entering mainstream production. The first three papers in this session focus on bulk 45nm technology with emphasis on low power and high performance stressing aggressive SRAM density increases and incorporation of new gate stack materials to drive device performance. The fourth paper extends 45nm SOI platform technology with the enablement of record-setting RF CMOS performance with peak fT of 485GHz for NFET and 345GHz for PFET. The invited paper in this session addresses the technology elements and their value proposition needed to achieve a comprehensive common platform offering for ASICs and foundry applications. The final two papers are the first looks into 32nm technology from both the low power bulk SoC and fully-depleted SOI perspectives pushing SRAM bitcell sizes to 0.15mm.