Philip A. Fisher

Is gate line edge roughness a first-order issue in affecting the performance of deep sub-micro bulk MOSFET devices?

An experimental study of the effects of gate line edge roughness (LER) on the electrical characteristics of bulk MOSFET devices was performed. Device simulation had previously predicted that gate LER causes off-state current to increase. In our experiments, gate LER was deliberately introduced in devices with 40 nm or longer physical gate length, and we found about 3X I/sub OFF/ increase (for 40 nm gate length) in the I/sub OFF/-I/sub ON/ plot. In our devices, Source/Drain (S/D) extensions are produced by implants self-aligned to gate edges. Simulation results indicate that what really matters is the roughness induced of the S/D to channel junctions by gate LER. Implantation scattering and dopant diffusion cause the S/D to channel junctions to be smoother than the gate edges. This will partially reduce the differences in the I/sub OFF/-I/sub ON/ curves caused by differing amounts of gate LER. By optimizing our process flows, we obtained a minimized gate LER (EdgeRMS<2 nm). We believe that the consequence of this minimized LER is secondary to the impact of other process variations across wafer for devices with 40 nm or longer gate length.

Gate line-edge roughness effects in 50-nm bulk MOSFET devices

We studied gate line edge roughness (LER) and its effect on electrical characteristics of 50nm bulk MOSFETs. Using simulation, we studied the underlying mechanism of three significant LER effects on the electrical performance of advanced 50 nm gate length bulk devices. First, we found that off-state leakage current is much more sensitive than the on-state drive current to gate LER. Second, we found that high frequency LER can lead to a decrease in effective channel length by enhanced lateral diffusion of the self-aligned source/drain extension. Third, low frequency LER causes local CD variation simply due to the statistical variation of average CD in a finite width sample. We also show how device design parameters, such as halo implant dose, can be used to tradeoff LER sensitivity and device performance.

Fast Transistor Threshold Voltage Measurement Method for High-Speed, High-Accuracy Advanced Process Characterization

As process technologies continually advance, process variation has greatly increased and has gradually become one of the most critical factors for IC manufacturing. Furthermore, these increasingly complex processes continue to make greater use of stressors for mobility enhancement, thus requiring large volumes of data for extensive characterization of layout-dependent effects (LDE) for validation of both SPICE models and design for manufacturing. Transistor threshold voltage (Vt) is a commonly used parameter both for characterization during process development and for monitoring of volume manufacturing. To adequately quantify local process variation or LDE, Vt must be measured for a sufficiently large number of device-under-tests (DUTs) to obtain a statistically representative sample population. The number of Vt measurements required to obtain such a statistically significant result, however, requires extremely long testing time, especially for array-based test structure designs including thousands of DUTs. In this paper, we present a very fast threshold voltage measurement methodology using an operational amplifier-based source-measure unit test configuration, which greatly improves testing efficiency and accuracy, and is not sensitive to process variation. The proposed test methodology can improve Vt testing time by a factor of 5-10 relative to the commonly used binary-search algorithm, and by a factor of ~2 relative to an optimized interpolation algorithm, and achieves better accuracy (standard deviation of Vt = 0.15 mV, versus typical accuracy of ~ 0.5 mV for the two algorithms mentioned). Furthermore, the layout and configuration of conventional test structures need not be modified to adapt the proposed methodology. The measured results from the most advanced process technology nodes demonstrate the testing efficiency and accuracy of the proposed test structure in characterizing the large number of DUTs required for quantifying process variation or LDEs.

A Novel Array-Based Test Methodology for Local Process Variation Monitoring

As process technologies continually advance, local process variation has greatly increased and gradually become one of the most critical factors for IC manufacturing. To monitor local process variation, a large number of DUTs (device-under-test) in close proximity must be measured. In this paper, we presents a novel array-based test structure to characterize local process variation with limited area overhead. The proposed test structure can guarantee high measurement accuracy by utilizing the proposed hardware IR compensation and voltage bias elevation. Furthermore, the DUT layout need not be modified for the proposed test structure so that the measured variation exactly reflects the reality in the manufacturing environment. The measured results from the few most advanced process-technology nodes demonstrate the effectiveness and efficiency of the proposed test structure in quantifying local process variation.

High Performance 65nm SOI Transistors Using Laser Spike Annealing

In this paper we present enhancements in transistor performance and manufacturability of a high performance 65nm node SOI transistor by the combination of reduced RTA temperature and laser spike anneal (LTRTA+LSA) achieved through simultaneous optimization of offset spacer and extension/halo. DC NFET drive current is increased by 10% to a value of 1120 muA/mum (1220muA/mum if 9% NFET SOI self-heating effect included) at 200nA/mum off-state current and VDD of 1.0V. PMOS drive current is enhanced by 5% to a value of 575muA/mum (60OmuA/mum if 5% PFET SOI self-heating effect included) which is less than enhancement observed in the NFET due to the differing amount of enhancement of capacitive inversion thickness (TINV) at short channel. With respect to circuit and product performance, this device provides a 5% delay improvement for a product-like ring-oscillator (RO) and results in an improved cross-die statistical distribution of RO delay time. The minimum stable SRAM operating voltage (Vmin) is also significantly improved, indicating that control of the overlap capacitance (Cov) may play a significant role in determining SRAM Vmin. For the first time, we report that the NFET Tinv reduction by LSA is substantially larger at shorter channel lengths which explains the large NFET drive current enhancements obtained by LSA

Mask versus Schematic - an enhanced design-verification flow for first silicon success

Layout versus Schematic (LVS) is a commonly used technique employed at the design stage to insure the correctness of physical layout. However, as process technologies continually advance, increasingly complex boolean operations are required to produce the desired on-mask patterns, which are frequently optimized to enhance transistor performance and process margin. Design layout which has been verified by LVS may undergo substantial layout changes when subjected to the mask generation booleans, with potential implications for performance and margin estimation, particularly given the aggressive use of stressors in modern CMOS technologies. Errors in mask generation booleans, which are very difficult to detect by present primitive inspection methods, can easily result in functional failure although the initial LVS predicted success. Therefore, LVS performed at the design stage is no longer an iron-clad guarantee of chip functionality in advanced process technologies. In this paper, we introduce Mask-versus-Schematic (MVS) verification, a novel design verification flow which directly compares the schematic netlist with a netlist extracted after application of all mask generation booleans, in order to insure the correctness of the final mask data just before tapeout. Furthermore, the introduced methodology can be performed using currently available physical verification EDA tools. The experimental results presented here, using examples from some of the industrys most advanced process technology nodes, demonstrate the effectiveness and efficiency of this methodology in detecting errors resulting from mask generation boolean operations.

A Novel Design Flow for Dummy Fill Using Boolean Mask Operations

Dummy fill has been demonstrated to be an effective technique to reduce process variation and improve manufacturability for advanced integrated circuit (IC) designs. However, the computation load, often several days for a realistic IC design, is a significant portion of the cycle time for delivering first silicon on new or modified designs. In this paper, we propose a novel design flow and dummy-fill algorithm based on Boolean operations, which greatly improves computational efficiency and pattern density uniformity, and enables dummy generation to be combined with the mask-preparation Boolean operations performed by the mask-fabrication facility. Mask data preparation can be performed in parallel with dummy generation and post-dummy simulation checks at the design house, resulting in improved first-silicon cycle time. Experimental results demonstrate these benefits in the context of an advanced foundry process technology.