Hideaki Tsuchiya
Renesas Electronics
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Featured researches published by Hideaki Tsuchiya.
international reliability physics symposium | 2011
Shinji Yokogawa; Satoshi Uno; Ichiro Kato; Hideaki Tsuchiya; Tatsuo Shimizu; Mitsuhiro Sakamoto
In this paper, we present the results of voltage-ramp dielectric breakdown and time-dependent dielectric breakdown experiments for contact-polysilicon control gate intra-level dielectric stacks. Lifetime distribution and area scaling are discussed statistically with the analysis of global and local space deviations using the electrical method. Optimized process reliability is evaluated by performing a SRAM lifetime test that measures the early life failure rate.
STRESS-INDUCED PHENOMENA IN METALLIZATION: Seventh International Workshop on Stress-Induced Phenomena in Metallization | 2004
Shinji Yokogawa; Hideaki Tsuchiya
This paper presents scaling impacts on electromigration‐induced mass transport in narrow single damascene Cu interconnects. The Kawasaki‐Hu test structure was used to investigate such impacts. Line widths ranging from 0.12 μm to 0.20 μm were used to demonstrate the scaling impact that is due to the electromigration‐induced diffusion. Lifetime that is determined by resistance degradation decreases according to the decreasing line width at a fixed current density. This is caused by decrease of the effective incubation time and increase of the drift velocity. A product of drift velocity and a square line width has a linear dependence on current density. The activation energy is 1.2 eV for the effective incubation time, and is 1.1 eV for the drift velocity, respectively. They are independent of the line width. The activation energy suggests that the effective incubation time is the time to void growth from the Cu/SiCN interface to trench bottom through Cu grain boundaries. The grain boundaries provide nucleat...
international reliability physics symposium | 2016
T. Shimizu; Naohito Suzumura; K. Ohgata; Hideaki Tsuchiya; H. Aono; M. Ogasawara
We investigated the time-dependent clustering (TDC) model for time-dependent dielectric breakdown (TDDB) of non-uniform dielectrics and revealed for the first time that the TDC model is a compound Weibull model that is expressed as a superposition of Weibull distributions. The Weibull model has two statistical parameters, scale parameter η and shape parameter β We clarified the precondition that the TDC model holds when term ηβ of the Weibull model is distributed according to an inverse-gamma distribution. By using our finding, we proposed a new method to directly estimate the variations of electric field and effective space from TDDB data. We found that the corresponding electric field distribution is a generalization of extreme value distribution, which is a natural consequence since the lifetime is determined by the maximum value of the electric field.
STRESS‐INDUCED PHENOMENA IN METALLIZATION: Ninth International Workshop on Stress‐Induced Phenomena in Metallization | 2007
Shinji Yokogawa; Hideaki Tsuchiya
To study of the impurity effect of electromigration kinetics, we have investigated the effects of Al doping in Cu interconnects. The effects of Al doping on the incubation time, drift velocity, and critical product of electromigration were investigated. The drift velocity of Cu mass transport in CuAl alloys decreases with an increase in the concentration of Al atoms. The observed critical product of electromigration is 1500 A/cm, and it is independent of the Al concentration. The activation energy of the normalized drift velocity increases with an increase in Al concentration. The Al concentrations at Cu/SiCN interface, grain boundary, Ta/Cu interface, and bulk were investigated along the length of a line by the electron microprobe technique. The time dependent Al concentration at the Cu/SiCN interface near the cathode end of the line is observed. These characteristics indicate that the doped Al affects the electromigration‐induced Cu diffusion and does not affect the driving force.
international interconnect technology conference | 2011
Hideaki Tsuchiya; Shinji Yokogawa; Hiroyuki Kunishima; T. Kuwajima; Tatsuya Usami; Y. Miura; K. Ohto; Kunihiro Fujii; M. Sakurai
The moisture absorption impacts on electromigration (EM) and time-dependent dielectric breakdown (TDDB) were investigated in Cu alloy/low-k interconnects. A long queue time (Q-time) has a serious impact on kinetics of both EM and TDDB characteristics. The moisture absorption causes the loss of alloy effects on EM lifetime improvements. The ultra-thin SiN (UT-SiN) remarkably suppresses the moisture absorption impacts due to Q-time. It also improves kinetics degradations of EM and TDDB that depend on the moisture absorption to low-k.
international interconnect technology conference | 2011
Daisuke Oshida; Ippei Kume; Hiroyuki Kunishima; Hideaki Tsuchiya; Hirokazu Katsuyama; M. Ueki; Manabu Iguchi; Shinji Yokogawa; Naoya Inoue; Noriaki Oda; M. Sakurai
Effects of post-etching treatment (PET) in trench patterning and re-sputtering in barrier metal sputtering on low-k/Cu interconnects were investigated for the low-k of Molecular Pore Stacking (MPS). Optimized combination of PET and re-sputtering reduces wiring capacitance by 5% due to well controlled profile, resulted from hardening effect of the exposed MPS at the trench bottom. The developed process sequence achieves 10 times loger EM lifetime and eliminates early failure mode in the TDDB test. Thus, the novel process, featuring PET and re-sputtering, contributes to highly reliability for 28 nm node CMOS and beyond.
international interconnect technology conference | 2011
Tatsuya Usami; Y. Miura; Tomoyuki Nakamura; Hideaki Tsuchiya; C. Kobayashi; K. Ohto; S. Hiroshima; M. Tanaka; Hiroyuki Kunishima; I. Ishizuka; T. Kuwajima; M. Sakurai; Shinji Yokogawa; Kunihiro Fujii
A highly reliable Enhanced Nitride Interface (ENI) process of barrier Low-k using an Ultra-Thin SiN (UT-SiN) has been developed for 40-nm node and beyond. The UT-SiN (3nm) has a good thickness uniformity and a good stability against absorption. By using this technique, a lower effective k and good via yields were obtained. In addition, 5x via electro-migration (EM) improvement, 50x TDDB and no SIV failure by 1000h were obtained in comparison to the conventional SiCN bi-layer process. And the ENI was analyzed by XPS and TOF-SIMS. According to these analyses, the mechanism for performance enhancement is proposed.
Microelectronic Engineering | 2013
Hideaki Tsuchiya; Shinji Yokogawa; Hiroyuki Kunishima; T. Kuwajima; Tatsuya Usami; Y. Miura; K. Ohto; Kunihiro Fujii; M. Sakurai
Archive | 2009
Shinji Yokogawa; Hideaki Tsuchiya
Archive | 2007
Hideaki Tsuchiya; Shinji Yokogawa