Masahide Inuishi

Novel NICE (nitrogen implantation into CMOS gate electrode and source-drain) structure for high reliability and high performance 0.25 /spl mu/m dual gate CMOS

We have proposed a novel structure with high reliability and high performance by nitrogen implantation into gate electrode and source-drain region for 0.25 /spl mu/m dual gate CMOS. It was found that the hot carrier resistance of both N-ch and P-ch MOSFETs can be effectively improved by incorporating nitrogen into the gate oxide with nitrogen implantation on the poly silicon gate. Moreover it was found that Ti-salicided shallow junction for 0.25 /spl mu/m CMOS can be successfully formed without increasing the junction leakage current.<<ETX>>

Effect of channel direction for high performance SCE immune pMOSFET with less than 0.15 /spl mu/m gate length

A high performance CMOSFET with a channel along the <100> crystallographic axis has been developed. Current drivability of the pMOSFET is improved by about 15% by changing the channel direction from <110> to <100> due to an increase in hole mobility and high immunity against short channel effects (SCE). As a result, a drive current of 810 /spl mu/A//spl mu/m for nMOS and of 420 /spl mu/A//spl mu/m for pMOS with 0.14 /spl mu/m gate length has been achieved under 1 nA//spl mu/m off current at 1.8 V operation.

The effects of nitrogen implantation into P/sup +/ poly-silicon gate on gate oxide properties

We have studied the effects of nitrogen implantation into P/sup +/ poly-silicon gate on gate oxide properties in detail for the surface channel PMOS below 0.25 /spl mu/m. It was founded that boron penetration through the gate oxide film can be effectively suppressed by nitrogen implantation into P/sup +/ poly-silicon gate. Moreover the generation of interface states and traps can be also reduced by nitrogen implantation. Therefore the resistance against the hot carrier injection can be dramatically improved. These improvements would be due to the incorporation of nitrogen into gate oxide film and the reduction of boron and fluorine atoms in the gate oxide film.<<ETX>>

Impact of surface proximity gettering and nitrided oxide side-wall spacer by nitrogen implantation on sub-quarter micron CMOS LDD FETs

We propose an advanced sub-quarter micron CMOS process for ultra shallow junctions and high reliability using a new nitrogen implantation technique. Nitrogen atoms implanted into the source/drain for NMOSFETs and PMOSFETs can suppress impurity diffusion and leakage current, since not only can nitrogen atoms occupy the diffusion path of arsenic and boron atoms but also the secondary defects induced by nitrogen implantation can act as a surface proximity gettering site. Moreover, this technique can remarkably suppress the hot carrier degradation for CMOS LDD FETs, since the segregation of nitrogen at interface between the substrate and the side-wall SiO/sub 2/ can reduce the interface state generation under the side-wall spacer.

Impact of the two traps related leakage mechanism on the tail distribution of DRAM retention characteristics

Two traps related leakage mechanism is proposed to explain the tail distribution of the DRAM retention characteristics. The main mode is explained by the trap assisted tunneling with one trap. We propose that the tail mode is created when the two traps are close enough to cooperate for increasing the leakage current. We calculate both the main and the tail distributions with the Monte Carlo method by using one basic equation deduced from our model for the first time.

Graded-junction gate/n/sup -/ overlapped LDD MOSFET structures for high hot-carrier reliability

A newly developed gate/n/sup -/ overlapped LDD MOSFET was investigated. The MOSFET was fabricated by an oblique rotating ion implantation technique. A formula for the impurity ion profile was derived to analyze the lowering of substrate current and improvement of the degradation caused by the hot-carrier effect of the MOSFET. It was proved that the impurity ion profile near the drain edge is remarkably graded in the directions along channel and toward substrate even just after the implantation, so that the maximum lateral electric field is relaxed as compared with conventional LDD MOSFETs. Also, the maximum point of the lateral electric field at the drain edge is located apart from the main path of the channel current. >

Low voltage operation of sub-quarter micron W-polycide dual gate CMOS with non-uniformly doped channel

A 0.25 /spl mu/m W-polycide dual gate CMOS has been newly developed for a logic in DRAM under low voltage operation. A novel gate electrode can eliminate inter-diffusion and the gate depletion using a barrier oxide film against dopant diffusion, so that a dual gate CMOS can be fabricated with sufficient thermal budget. Moreover, low threshold voltage and high current drivability can be obtained by a non-uniformly doped channel structure formed by the oblique rotational ion implantation utilizing W-polycide gate as a mask. As a result, a high performance has been achieved.

80 nm CMOSFET technology using double offset-implanted source/drain extension and low temperature SiN process

Double offset-implanted source/drain extension and 550/spl deg/C silicon nitride deposition for sidewall and borderless contact have been applied to sub-0.1 /spl mu/m CMOS for improvement of short channel effect as well as parasitic resistance. Consequently, 830/400 /spl mu/A//spl mu/m drive current with 2.5 nm gate insulator has been achieved under 1 nA//spl mu/m off-leakage at 1.5 V operation with short channel tolerance to 80 nm gate length.

Gate capacitance characteristics of gate N/sup -/ overlap LDD transistor with high performance and high reliability

The authors present the gate capacitance characteristics of the gate/N/sup -/ overlap LDD (lightly doped drain) transistor. The gate capacitance was directly measured by a four-terminal method, using an LCR meter. The measured results for the overlap LDD were compared with those for the single drain and the LDD structure. It was demonstrated that the gate/drain capacitance for the overlap LDD is smaller than that for the single drain and as small as that for the LDD in spite of the large overlap length between the gate and the N/sup -/ region. This result was also confirmed by simulation, which indicates that the small gate/drain capacitance of the overlap LDD is due to the depletion of the N/sup -/ drain under the gate by the normal electric field from the gate and the lateral electric field at the drain.<<ETX>>

A high performance and highly reliable dual gate CMOS with gate/n/sup -/ overlapped LDD applicable to the cryogenic operation

A dual-gate CMOS structure has been developed which features an overlap LDD (lightly doped drain) NMOS with n/sup +/ poly gate and a surface channel PMOS with p/sup +/ poly gate whose source/drain and gate were salicided with low-resistance TiSi/sub 2/. The gate/n/sup -/ overlapped structure was fabricated by rotational oblique ion implantation. This CMOS structure can realize low-supply-voltage operation due to the small absolute value of threshold voltage without punchthrough. It is demonstrated that, using the overlap LDD NMOS, the circuit speed and the reliability can be improved, compared with the single and the conventional LDD NMOS. The cryogenic operation of the structure is examined.<<ETX>>