Takashi Kuroi

Novel NICE (nitrogen implantation into CMOS gate electrode and source-drain) structure for high reliability and high performance 0.25 /spl mu/m dual gate CMOS

We have proposed a novel structure with high reliability and high performance by nitrogen implantation into gate electrode and source-drain region for 0.25 /spl mu/m dual gate CMOS. It was found that the hot carrier resistance of both N-ch and P-ch MOSFETs can be effectively improved by incorporating nitrogen into the gate oxide with nitrogen implantation on the poly silicon gate. Moreover it was found that Ti-salicided shallow junction for 0.25 /spl mu/m CMOS can be successfully formed without increasing the junction leakage current.<<ETX>>

The effects of nitrogen implantation into P/sup +/ poly-silicon gate on gate oxide properties

We have studied the effects of nitrogen implantation into P/sup +/ poly-silicon gate on gate oxide properties in detail for the surface channel PMOS below 0.25 /spl mu/m. It was founded that boron penetration through the gate oxide film can be effectively suppressed by nitrogen implantation into P/sup +/ poly-silicon gate. Moreover the generation of interface states and traps can be also reduced by nitrogen implantation. Therefore the resistance against the hot carrier injection can be dramatically improved. These improvements would be due to the incorporation of nitrogen into gate oxide film and the reduction of boron and fluorine atoms in the gate oxide film.<<ETX>>

Stress analysis of shallow trench isolation for 256 M DRAM and beyond

The stress generation of the shallow trench isolation has been systematically investigated using the stress simulation and the experiment. It is found that the scale-down of the isolation pitch causes a remarkable stress generation due to the overlap of the stress from both trench sides. Therefore a small isolation pitch causes the crystal defects generation with ease. We carried out the stress analysis against the various process parameters in detail. The high temperature sacrificial oxidation can effectively eliminate the stress generation. It was confirmed that enough isolation characteristics can maintain up to 0.1 /spl mu/m regime to give a careful consideration of the stress reduction.

Impact of surface proximity gettering and nitrided oxide side-wall spacer by nitrogen implantation on sub-quarter micron CMOS LDD FETs

We propose an advanced sub-quarter micron CMOS process for ultra shallow junctions and high reliability using a new nitrogen implantation technique. Nitrogen atoms implanted into the source/drain for NMOSFETs and PMOSFETs can suppress impurity diffusion and leakage current, since not only can nitrogen atoms occupy the diffusion path of arsenic and boron atoms but also the secondary defects induced by nitrogen implantation can act as a surface proximity gettering site. Moreover, this technique can remarkably suppress the hot carrier degradation for CMOS LDD FETs, since the segregation of nitrogen at interface between the substrate and the side-wall SiO/sub 2/ can reduce the interface state generation under the side-wall spacer.

Advanced shallow trench isolation to suppress the inverse narrow channel effects for 0.24 /spl mu/m pitch isolation and beyond

A novel shallow trench isolation (STI) technique named Poly-Si-Buffered-mask STI (PB-STI) using the SiN/poly-Si/SiO/sub 2/ stacked mask has been proposed. The poly-Si is oxidized at the step of liner oxidation and then a small birds beak is grown. With small birds beak formation the oxide recess at the trench edge is prevented and the fringing of electric-field from the gate electrode can be effectively avoided. PB-STI can completely suppress the inverse narrow channel effect with quite simple process sequence which includes no corner implantation.

0.15 /spl mu/m CMOS process for high performance and high reliability

We have developed a novel 0.15 /spl mu/m CMOS process for high performance and high reliability, consisting of mixing the CoSi/sub 2/-Si interface using Si/sup +/ implantation to form shallow junctions, nitrogen implantation into gate electrodes to improve the oxide reliability, and selective channel implantation using a gate-around mask to reduce the junction capacitance. By using these processes, the propagation delay time of 21 psec/stage was obtained for a 0.15 /spl mu/m CMOS ring oscillator at the allowable maximum supply voltage of 2.0 V limited by hot-carrier degradation.<<ETX>>

Low voltage operation of sub-quarter micron W-polycide dual gate CMOS with non-uniformly doped channel

A 0.25 /spl mu/m W-polycide dual gate CMOS has been newly developed for a logic in DRAM under low voltage operation. A novel gate electrode can eliminate inter-diffusion and the gate depletion using a barrier oxide film against dopant diffusion, so that a dual gate CMOS can be fabricated with sufficient thermal budget. Moreover, low threshold voltage and high current drivability can be obtained by a non-uniformly doped channel structure formed by the oblique rotational ion implantation utilizing W-polycide gate as a mask. As a result, a high performance has been achieved.

Self-gettering and proximity gettering for buried layer formation by MeV ion implantation

The authors studied the characteristics of the junction leakage current of diodes having a buried layer formed by high-energy boron, phosphorus, and arsenic implantation. A remarkable decrease in junction leakage current to the level comparable to that without a buried layer was observed with doses of over 3*10/sup 14/ ions/cm/sup 2/ (self-gettering). The effects of additional high-energy carbon, oxygen, and fluorine implantation on the buried layer were also investigated. A strong gettering effect in reducing the leakage current of the diode was found (proximity gettering). The gettering by secondary defects induced by high-energy ion implantation is found to be a major cause of these phenomena.<<ETX>>

Channel engineering in sub-quarter-micron MOSFETs using nitrogen implantation for low voltage operation

Considerable reduction in the threshold voltage for sub-quarter-micron NMOSFETs can be achieved along with suppression of the short channel effects by only adding nitrogen implantation into the channel region. Moreover this simple process can improve hot carrier degradation. The superior performance is based on the effective acceptor concentration drop at the surface of the channel region as well as the light nitridation of the gate oxide and the side-wall spacer.

Highly reliable 0.15 /spl mu/m MOSFETs with Surface Proximity Gettering (SPG) and nitrided oxide spacer using nitrogen implantation

An advanced nitrogen implantation technique is proposed. The new technique can suppress remarkably the hot carrier degradation. Since the generation of interface states can be reduced by the incorporation of nitrogen at the interface between a substrate and SiO/sub 2/ spacers. Moreover, the ultra shallow junction without the increase in leakage current can be formed by nitrogen implantation into the source/drain. Since the secondary defects induced by nitrogen implantation can act as a surface proximity gettering (SPG) site.