Hideki Tsuya

Selective Silicon Epitaxy Using Reduced Pressure Technique

Silicon selective epitaxial growth using the SiH2Cl2–HCl–H2 system was successfully accomplished on a window surrounded by fine patterned insulator films as a mask. Surface planarity was obtained at less than 80 Torr reduced pressure. Good selectivity was realized by suitable HCl injection during epitaxial growth. Moreover, it was found that the induced defect density on the epi-layer was less at lower growth temperature.

Advanced Techniques to Decrease Defect Density in Molecular Beam Epitaxial Silicon Films

Defect density dependence on various surface cleaning conditions for molecular beam epitaxial (MBE) silicon films was investigated. Defect-free films were obtained on (100) and (511) wafers, using a combination of ozone cleaning and predeposition process after the usual wet cleaning. On the (111) wafer, the defect density dependence on growth rate was examined. The two-step growth-rate procedure was effective in decreasing stacking faults on the (111) wafer. The difference in defect density between (100) and (111) wafers is also discussed.

Selective silicon epitaxial growth for device-isolation

Abstract Selective silicon epitaxial growth using the SiH 2 Cl 2 / HCl / H 2 system under reduced pressure was accomplished in windows surrounded by a fine patterned insulator film on a silicon substrate. Selectivity, surface planarity, and facet formation were studied as a function of growth pressure, growth temperature, and HCl flow rate during selective epitaxial growth. Defects, which were mostly pairs of stacking faults, were observed along sidewalls. The defect density in the epi-layer decreased with both decreasing growth temperature and increasing HCl flow rate. Electrical properties of p-n junctions fabricated in the epi-layers were investigated. Polysilicon gate MOSFETs were successfully fabricated on the epitaxial silicon layers. It was revealed that the selective epitaxial growth isolation was effective to reduce latch-up susceptibility for CMOS circuits. It has been discovered that the selective epitaxial growth is applicable to fine and deep isolation and can realize submicron geometry isolation for VLSI.

Behaviours of Thermally Induced Microdefects in Heavily Doped Silicon Wafers

Thermally induced microdefects in heavily doped silicon wafers are investigated. It has been shown that the generation of thermally induced microdefects is strongly affected by the type and concentration of dopants, and that microdefects necessary for intrinsic gettering are not easily generated in heavily doped n-type wafers. To generate the microdefects in heavily doped n-type wafers, an improved heat treatment procedure is developed. The observed results are discussed in terms of the difference of point defect density between p- and n-type wafers.

Present Status and Prospect of Si Wafers for Ultra Large Scale Integration

Si wafers have contributed to the rapid growth of the semiconductor industry as a basic material for ultra large scale integration (ULSI) through the research and development of new technologies and mass production in response to the various demands of device manufacturers. In this paper, first, the key issues of wafer quality improvement with respect to wafer fabrication technology, gettering and grown-in defects are reviewed. Various wafers currently in use such as annealed wafers, epitaxial wafers and 300 mm diameter wafer are discussed with respect to technology and cost effectiveness. Advanced Si-based wafers represented by silicon on insulator (SOI) and strained SiGe wafers are also described. After discussing the challenge to develop innovative Si wafer technologies which will lead to the future development of ULSI, the other important issues associated with Si wafers such as the re-examination of over-stringent specifications, cost reduction, economically reasonable pricing and the promotion of mutual understanding and cooperation between device makers and wafer makers for the continued development of both industries are emphasized.

Heterogeneous distribution of interstitial oxygen in annealed Czochralski‐grown silicon crystals

It is shown that interstitial oxygen infrared (IR) absorption at 515 cm−1 decreases anomalously compared with the absorption at 1106 cm−1 in heat‐treated Czochralski‐grown silicon wafers. This phenomenon is described by the close correlation between the absorption coefficient ratio αr (α1106/α515), the half‐bandwidth of the 1106‐cm−1 peak, and the precipitated oxygen content during heat treatments. As a result, it is suggested that on the basis of IR absorption spectrum data interstitital oxygen atoms distribute heterogeneously in a silicon matrix as the forestage of Si‐0 complex precipitation.

Formation of Grown-in Defects during Czochralski Silicon Crystal Growth.

The formation behavior of grown-in defects in Czochralski silicon (CZ-Si) crystals was investigated using two crystals that were quenched during growth but in one case after crystal growth had been halted for 5 h. The distributions of grown-in defect density and size, and their micro-structures were analyzed as a function of temperature during crystal growth just before quenching by means of an optical precipitate profiler (OPP) and an atomic force microscope (AFM) coupled with a laser particle counter. The formation of grown-in defects, which are considered to be octahedral voids, was found to consist of two dominant processes. The first step involves rapid void growth in a narrow temperature range of about 30° C below 1100° C and the subsequent step consists of an oxide film growth on the inner surface of the void during the cooling process to about 900° C after void formation. It was also found that the growth of the oxide film in the voids is rate-limited by the diffusion rate of oxygen atoms in silicon. In addition, it is strongly suggested that void formation in such a narrow temperature range is due to a rapid agglomeration of vacancies.

Gettering of Cu and Ni Impurities in SIMOX Wafers

The gettering of Cu and Ni impurities in intentionally contaminated SIMOX wafers have been studied by means of cross-sectional transmission electron microscopy, nanoprobe energy dispersive x-ray spectroscopy, secondary ion mass spectrometry, and selective etching. The wafers with Cu or Ni surface concentrations ranged from about 10 12 up to 10 17 atom/cm 2 were annealed at various temperatures followed by slow cooling to room temperature. Single and multistep thermal treatments were applied. It has been found that the buried oxide does not prevent the diffusion of both Cu and Ni contaminants from the top silicon layer into the bulk substrate at the whole investigated temperature range from 600 to 950°C. Moreover the effective gettering of Cu and Ni in the thin silicon substrate layer located just beneath the buried oxide has been observed and explained as being due to the heterogeneous impurity precipitation at stacking fault tetrahedra formed there during the SIMOX manufacturing. The gettering process has remained stable during the thermal simulation of CMOS device process of new generation ICs with 0.25 μm feature size.

Crystalline correlation of epitaxial Si films with underlying spinel films in Si/(MgO Al2O3) spinel/Si structure

Using epitaxial magnesia spinel (MgO Al2O3) films on (100) Si, heteroepitaxial Si films (0.6–3 μm) on these substrates are obtained by a conventional chemical vapor deposition method. The crystallinity of both epitaxial Si and spinel films was investigated by x‐ray diffraction techniques. Silicon film quality becomes more perfect on thinner spinel films with smoother surfaces in the range of more than ∼0.1 μm, in spite of the spinel crystal perfection becoming inferior with decreasing film thickness. These results are discussed in terms of the spinel surface roughness effect on Si nuclei coalescence.

Novel device isolation technology with selective epitaxial growth

A novel device isolation technology for small geometry VLSIs using selective epitaxial growth is described. This isolation structure is composed of an SiO2insulator and an epitaxial silicon selectively grown on a bulk silicon surface surrounded with an SiO2isolation wall using a reduced pressure SiH2Cl2-H2-HCl system. This technology, called SEG (selective epitaxial growth) isolation, offers the potential of both fine and deep isolation with submicrometer size features. Polysilicon gate MOSFETs are successfully fabricated on the epitaxial silicon layer. The subthreshold slopes for p-channel or n-channel devices are confirmed to be consistent with these for conventional devices. Using SEG isolation technology, less channel width variation and small narrow-channel effect are shown by electrical characteristics for MOSFETs. The subthreshold behavior for parasitic field devices with submicrometer geometry gives results applicable to fine isolation.