Akihiko Ishitani

SiO2 / Si Interface Structures and Reliability Characteristics

This paper shows that a structural transition layer of SiO 2 exists at an SiO 2 /Si interface prepared by thermal oxidation of Si. Using a newly developed grazing-incidence x-ray diffraction of synchrotron radiation, the transition layer density (2.4 g/cm 3 ) is found to be lower than the immediate bulk SiO 2 density (2.6 g/cm 3 ), and its thickness is approximately 7 nm. Electrical properties of the SiO 2 , films are examined by using Fowler-Nordheim tunneling electrons which are injected from the polycrystalline silicon gate electrode into the SiO 2 film. The injected charge-to-breakdown (Qbd) rapidly degrades when the SiO 2 film thickness decreases below approximately 7 nm due to dielectric breakdown in the transition layer. Based on theoretical analysis, the mechanism of the dielectric breakdown in the transition layer is proposed to be Si-Si bond formations via hypervalent Si atoms and a replacement reaction of an oxygen atom with an electron. Introduction of nitrogen atoms into the transition layer improves the Qbd degradation of thin SiO 3 films, because the Si-Si bond formation is suppressed by stress relaxation in the transition layer

Structural and electrical characterization of SrTiO3 thin films prepared by metal organic chemical vapor deposition

SrTiO3 thin films were prepared on Si and Pt/TaOx/Si substrates by Sr(DPM)2/Ti(i-OC3H7)4/O2/Ar chemical vapor deposition (CVD), using a simple vaporizing-and-transport source delivery system. A thickness uniformity of ±5.6% and a composition uniformity of ±2.7% were obtained. The dielectric constant was 210 for 110 nm thick SrTiO3 films (Sr/(Sr+Ti)=0.5) annealed at 600°C for 2 hours. An SiO2 equivalent thickness of 1.1 nm was obtained for 40 nm thick SrTiO3 films, and leakage current densities were 6×10-8 A/cm2 at 1.0 V and 5×10-7 A/cm2 at 1.65 V. The structural and electrical properties were affected by the film composition.

Facet Formation in Selective Silicon Epitaxial Growth

Facets observed adjacent to insulator films in selective silicon epitaxial growth were studied. The facet formation depended on the crystallographic orientation of the openings, and facets did not appear adjacent to the SiO2 sidewall parallel to the [100] direction. Facet formation could also be suppressed by using a polysilicon-coated sidewall. Defects in the selective epi-layers were examined using transmission electron microscopy, and facet-free and defect-free epilayers were obtained.

Selective silicon epitaxial growth for device-isolation

Abstract Selective silicon epitaxial growth using the SiH 2 Cl 2 / HCl / H 2 system under reduced pressure was accomplished in windows surrounded by a fine patterned insulator film on a silicon substrate. Selectivity, surface planarity, and facet formation were studied as a function of growth pressure, growth temperature, and HCl flow rate during selective epitaxial growth. Defects, which were mostly pairs of stacking faults, were observed along sidewalls. The defect density in the epi-layer decreased with both decreasing growth temperature and increasing HCl flow rate. Electrical properties of p-n junctions fabricated in the epi-layers were investigated. Polysilicon gate MOSFETs were successfully fabricated on the epitaxial silicon layers. It was revealed that the selective epitaxial growth isolation was effective to reduce latch-up susceptibility for CMOS circuits. It has been discovered that the selective epitaxial growth is applicable to fine and deep isolation and can realize submicron geometry isolation for VLSI.

Mechanism of leakage current through the nanoscale SiO2 layer

We clarify the mechanism of leakage current through the nanoscale ultrathin silicon dioxide (SiO2) layer in a metal‐insulator‐semiconductor structure based on the multiple scattering theory when technologically important phosphorus doped polycrystalline silicon is adopted as the gate electrode. We also derive an analytic expression for the direct tunneling current, and show that its measurement presents an excellent opportunity to determine the effective mass of an electron in the SiO2.

Chemical Vapor Deposition of ( Ba , Sr ) TiO3

SrTiO 3 and (Ba, Sr)TiO 3 thin films were fabricated on Si and Pt/TaO 2 /Si substrates by chemical vapor deposition (CVD) using Sr(DPM) 2 , Ba(DPM) 2 , Ti(O-i-C 3 H 7 ) 4 , and O 2 where DPM is dipivaloylmethanate or formally 2,2,6,6-tetramethyl-3,5-heptanedionate. The deposition system was operated in both thermal CVD mode and electron cyclotron resonance (ECR) plasma CVD mode. Variations in individual Sr and Ti deposition rates with differing deposition conditions were investigated. The SrTiO 3 and (Ba, Sr)TiO 3 films were characterized with a view to discussing the step-coverage, crystal structure, and electrical properties. The step-coverage over the 300 nm wide SiO 2 lines, with 500 nm height and 500 nm spacing, was 30 to 40%. The 40 to 100 nm SrTiO 3 films, through the postdeposition annealing process, showed dielectric constants >140 with a leakage current density level <10 -7 A/cm at 1 V. The prospects for applying the CVD (Ba, Sr)TiO 3 films to giga-bit dynamic random access memory storage capacitors are discussed

Theoretical Calculation of Photoabsorption of Various Polymers in an Extreme Ultraviolet Region

We have calculated the linear absorption coefficients of various resist polymers using the mass absorption coefficients at 13 nm and the density obtained from the graph-theoretical treatment derived by Bicerano. The values indicate that the transmittance at 13 nm of conventional resists used in 193-nm, 248-nm and 365-nm lithography is about 30% when the thickness is 3000 A and 60–70% when it is 1000 A. This shows that conventional resists are suitable for an EUVL (extreme ultraviolet lithography) thin-layer resist (TLR) process using a hard-mask layer, but their large photoabsorption makes them unsuitable for a single-layer resist (SLR) process. To design polymers that are suitable for an SLR process, we further calculated the absorption of about 150 polymers. The results suggest that the introduction of aromatic groups into a polymer not only reduces the absorption at 13 nm but also increases the etching resistance.

Ultrathin silicon nitride films prepared by combining rapid thermal nitridation with low‐pressure chemical vapor deposition

Ultrathin silicon nitride films were prepared using rapid thermal nitridation prior to low‐pressure chemical vapor deposition (RTN+LPCVD). The low‐field leakage current of the 4.5‐nm‐thick film was found to be significantly reduced to a value of 10−8 A/cm2 at 4 MV/cm. Additionally, the time needed for 50% of the films to show dielectric failures was extended by about 20 times, relative to conventional LPCVD silicon nitride films. These improvements in electrical characteristics may be attributed to the low interface oxygen concentration as determined by secondary‐ion mass spectroscopy and x‐ray photoelectron spectroscopy. The RTN+LPCVD films are very suitable for use in future dynamic‐random‐access memories.

A high capacitive-coupling ratio (HiCR) cell for 3 V-only 64 Mbit and future flash memories

A novel contactless cell with high capacitive-coupling ratio (HiCR) of 0.8, which is programmed and erased by Fowler-Nordheim tunneling, has been developed for 3 V-only 64 Mbit and future flash memories. A 1.50 /spl mu/m/sup 2/ cell area is obtained by using a 0.4 /spl mu/m technology. The HiCR cell structure is realized by 1) self-aligned definition of small tunneling regions underneath the floating-gate side wall and 2) advanced rapid thermal process for 7.5-nm thick tunnel oxynitride. The internal voltages used for program and erase are +8 V and +12 V, respectively. The total process-step numbers can be reduced to 85% compared to reported memory cells so far.<<ETX>>

Device Layer Transfer Technique using Chemi-Mechanical Polishing

A device layer transfer technique, a new technique for transferring a thin device layer fabricated on the silicon wafer onto an insulating substrate, is described. The fundamental processes supporting this technique are wafer thinning using chemi-mechanical polishing and wafer fastening. A 2 µm-thick device layer with a 2 inch diameter is formed on a quartz glass substrate without significant degradation in transistor characteristics.