Hiroshi Horie

Scaling theory for double-gate SOI MOSFET's

A scaling theory for double-gate SOI MOSFETs, which gives guidance for device design (silicon thickness t/sub si/; gate oxide thickness t/sub ox/) that maintains a subthreshold factor for a given gate length is discussed. According to the theory, a device can be designed with a gate length of less than 0.1 mu m while maintaining the ideal subthreshold factor. This is verified numerically with a two-dimensional device simulator. >

Ultrafast operation of V/sub th/-adjusted p/sup +/-n/sup +/ double-gate SOI MOSFET's

To optimize the V/sub th/ of double-gate SOI MOSFETs, we fabricated devices with p/sup +/ poly-Si for the front-gate electrode and n/sup +/ poly-Si for the back-gate electrode on 40-nm-thick direct-bonded SOI wafers. We obtained an experimental V/sub th/ of 0.17 V for nMOS and -0.24 V for pMOS devices. These double-gate devices have good short-channel characteristics, low parasitic resistances, and large drive currents. For gates 0.19 /spl mu/m long, front-gate oxides 8.2 nm thick, and back-gate oxides 9.9 nm thick, we obtained ring oscillator delay times of 43 ps at 1 V and 27 ps at 2 V. To our knowledge, these values are the fastest reported for this gate length with suppressed short-channel effects.<<ETX>>

Analysis of p/sup +/ poly Si double-gate thin-film SOI MOSFETs

The authors have fabricated planar p/sup +/ poly Si double-gate thin-film SOI (silicon-on-insulator) nMOSFETs using wafer bonding. The fabricated devices have shown a transconductance, Gm, exceeding twice that of the single-gate SOI-MOSFET. It was confirmed that conduction in the double-gate SOI MOSFET originates from a fully flat potential and charge injection. An analytical model developed by the authors has displayed electrical characteristics that agree well with those of the fabricated devices.<<ETX>>

Novel high aspect ratio aluminum plug for logic/DRAM LSIs using polysilicon-aluminum substitute (PAS)

This paper describes a polysilicon-aluminum substitute (PAS) technique for single-crystalline aluminum plugs with aspect ratios of over 7 used for subquartermicron logic/DRAM LSIs. A via hole was filled with polysilicon by CVD, and aluminum was deposited on the planarized polysilicon plug. An aluminum plug was substituted for the polysilicon by annealing. We filled via holes having a minimum diameter of 0.175 /spl mu/m and a depth of 1.7 /spl mu/mn (an aspect ratio of about 10) with aluminum.

Abnormal solid solution and activation behavior in Ga‐implanted Si(100)

Rapid thermal annealing (RTA) and furnace annealing of Ga‐implanted Si were studied. Ga atoms implanted into Si are located on substitutional lattice sites in concentration above the solid solubility limit after short‐time and low‐temperature annealing. Low‐resistivity shallow p+ junctions can be fabricated using this metastable layer. However, precipitation and redistribution of the Ga atoms were observed after high‐temperature or longer time annealing. Shallow p+ junctions fabricated by Ga implantation and RTA are suitable for submicron complementary‐metal‐oxide‐semiconductor devices.

Advanced Metal Oxide Semiconductor and Bipolar Devices on Bonded Silicon‐on‐Insulators

Silicon-on-insulator devices have problems with both performance and cost. We developed three advanced devices on bonded SOI produced using pulse-field-assisted bonding and selective polishing in an attempt to solve these problems. We tightly bonded highly implanted wafers, epitaxial wafers, and wafers covered with smoothed CVD oxide at temperatures below 1000 o C. We uniformly thinned bonded wafers by grinding, polishing, resistivity-sensitive etching, or selective polishing. We formed buried layers and buried electrodes by bonding and polishing techniques. Our high speed epitaxial-base transistor on 1-μm thick SOI has a cutoff frequency of 32 GHz

Thin-film quasi-SOI power MOSFET fabricated by reversed silicon wafer direct bonding

A quasi-SOI power MOSFET has been fabricated by reversed silicon wafer direct bonding. In this power MOSFET, the buried oxide under the channel and source regions is removed and the channel region is directly connected to the source body contact electrode to reduce the base resistance of the parasitic npn bipolar transistor. The quasi-SOI power MOSFET can suppress the parasitic bipolar action and shows lower specific on-resistance than that of the conventional SOI power MOSFET. The fabricated chip level quasi-SOI power MOSFET shows the specific on-resistance of 86 m/spl Omega//spl middot/mm/sup 2/ and on-state breakdown voltage of 30 V.

Giga-bit DRAM cells with low capacitance and low resistance bit-lines on buried MOSFETs and capacitors by using bonded SOI technology-reversed stacked capacitor (RSTC) cell

This paper describes a reversed-stacked-capacitor (RSTC) cell for Giga-bit DRAMs, where a storage capacitor and a MOSFET are reversed by using chemical-mechanical-polishing (CMP) and bonded-SOI technology. The virtual flat surface at the bottom of the MOSFET is made into a real surface by polishing. The bit-lines and metal wirings are realized on the flat surface with low-aspect-ratio contact holes throughout the whole chip. This cell structure is suitable for not only Giga-bit DRAMs but also embedded DRAMs. A test memory array is fabricated with a 64 Mbit DRAM design rule. Both capacitance and resistance of bit-lines decreased by a factor of two with this RSTC cell compared to the conventional shielded-bit-line STC cells. The bit-lines are placed far from word-lines and cell-capacitors. The bit-lines are made of low resistivity materials after all the high-temperature processes have been finished.

Ultrafast low-power operation of p/sup +/-n/sup +/ double-gate SOI MOSFETs

Using direct bonded SOI wafers just 40 nm thick, we fabricated p/sup +/-n/sup +/ double-gate SOI MOSFETs. These devices, with an appropriate Vth, have good short-channel behavior and a large drive current. For Lg=0.19 /spl mu/m, we obtained an inverter delay time of 43 ps at 1 V, and 27 ps at 2 V. These are the fastest reported values for this gate length. The high performance is attributed to the large drain current, the low series resistance, and the reduction of the parasitic drain junction capacitance.<<ETX>>

A nitride-isolated molybdenum-polysilicon gate electrode for MOS VLSI circuits

A new gate electrode structure is demonstrated. The low-resistive gate electrode consists of a triple layer of molybdenum and polysilicon films isolated with an ultrathin silicon-nitride film, namely MTP-metal/tunneling nitride/polysilicon. The tunneling nitride, which is grown by direct thermal nitridation of silicon, avoids silicidation of molybdenum and diffusion of impurities resulting in a thin SiO2film of good quality. Characteristics of discrete FETs can be designed like those of conventional silicon-gate devices. No instability due to the tun, neling nitride has been observed in both dc and high-speed switching operations. The technique is useful for MOS VLSI circuits.