Nobuhiro Endo

Ferroelectric field‐effect memory device using Bi4Ti3O12 film

A ferroelectric field‐effect transistor has been investigated using a thin film of bismuth titanate (Bi4Ti3O12) deposited on a Si substrate by rf sputtering. Achievement of the ferroelectric polycrystalline Bi4Ti3O12 films without any cracks necessitates postdeposition heat treatment in air at temperatures ?550 °C for 30 min. The film, heat treated at 650 °C, has a remanent polarization of 4.0 μC/cm2 and a coercive field of about 250 kV/cm at 1 kHz. A FET having a gate structure of Bi4Ti3O12‐SiO2‐Si was fabricated, where the SiO2 served to prevent charge injection from Si into the ferroelectric film. (This process would degrade the retention of memorized states.) The FET can be switched by voltages of as low as 15 V applied to the gate. The on and off states are very stable at room temperature.

Selective Silicon Epitaxy Using Reduced Pressure Technique

Silicon selective epitaxial growth using the SiH2Cl2–HCl–H2 system was successfully accomplished on a window surrounded by fine patterned insulator films as a mask. Surface planarity was obtained at less than 80 Torr reduced pressure. Good selectivity was realized by suitable HCl injection during epitaxial growth. Moreover, it was found that the induced defect density on the epi-layer was less at lower growth temperature.

Facet Formation in Selective Silicon Epitaxial Growth

Facets observed adjacent to insulator films in selective silicon epitaxial growth were studied. The facet formation depended on the crystallographic orientation of the openings, and facets did not appear adjacent to the SiO2 sidewall parallel to the [100] direction. Facet formation could also be suppressed by using a polysilicon-coated sidewall. Defects in the selective epi-layers were examined using transmission electron microscopy, and facet-free and defect-free epilayers were obtained.

Selective silicon epitaxial growth for device-isolation

Abstract Selective silicon epitaxial growth using the SiH 2 Cl 2 / HCl / H 2 system under reduced pressure was accomplished in windows surrounded by a fine patterned insulator film on a silicon substrate. Selectivity, surface planarity, and facet formation were studied as a function of growth pressure, growth temperature, and HCl flow rate during selective epitaxial growth. Defects, which were mostly pairs of stacking faults, were observed along sidewalls. The defect density in the epi-layer decreased with both decreasing growth temperature and increasing HCl flow rate. Electrical properties of p-n junctions fabricated in the epi-layers were investigated. Polysilicon gate MOSFETs were successfully fabricated on the epitaxial silicon layers. It was revealed that the selective epitaxial growth isolation was effective to reduce latch-up susceptibility for CMOS circuits. It has been discovered that the selective epitaxial growth is applicable to fine and deep isolation and can realize submicron geometry isolation for VLSI.

Device Layer Transfer Technique using Chemi-Mechanical Polishing

A device layer transfer technique, a new technique for transferring a thin device layer fabricated on the silicon wafer onto an insulating substrate, is described. The fundamental processes supporting this technique are wafer thinning using chemi-mechanical polishing and wafer fastening. A 2 µm-thick device layer with a 2 inch diameter is formed on a quartz glass substrate without significant degradation in transistor characteristics.

Silicon Selective Epitaxial Growth and Electrical Properties of Epi/Sidewall Interfaces

Facet formation and stacking fault generation in silicon selective epitaxial growth are studied. On selective epilayer surfaces, a {311} facet and a {111} microfacet are formed on a {100} and a {111} substrate, respectively. In selective epilayers, stacking faults are observed adjacent to the sidewall Facet-free and stacking-fault-free selective epilayers are obtained using the -orinted sidewall at low growth temperatures. These results are explained by an epitaxial growth model at hollow bridge sites. Electrical properties of the interfaces between the selective epilayer and the sidewall are also studied. The -oriented SiO2 sidewall has better electrical characteristics than other sidewall orientations and sidewall materials.

Crystalline Defects in Selectively Epitaxial Silicon Layers

Crystalline defects in selectively epitaxial silicon layers have been studied as a function of growth parameters, especially growth temperature and HCl flow rate injected in the SiH2Cl2–H2 system, for (100)- and (111)-substrates. Defects, which were mostly pairs of stacking faults, were observed along the sidewall. The defect density in the epitaxial layer decreased with both increasing HCl flow rate and decreasing growth temperature. Electrical property of the epitaxial layer was also improved with decreasing growth temperature.

Device layer transferred poly-Si TFT array for high resolution liquid crystal projector

An active-matrix liquid-crystal light valve (LCLV) for a high-resolution projector, using device layer transfer technology, is proposed. This LCLV will not require high-density interconnection between bus lines and Si IC drivers. To confirm the validity of this proposal, a high-performance poly-Si TFT (thin-film transistor) array with 480*768 pixels in 80 mm diagonal has been fabricated on an oxidized Si wafer. This TFT has a triple-gate structure for obtaining a high on/off current ratio and buried-isolated-pixel-electrode (BIP) structure and ITO barrier metal for reducing defects. This TFT array was transferred onto transparent glass substrate using device layer transfer technology, and the liquid-crystal projector was successfully realized.<<ETX>>

Lattice defect in selective epitaxial silicon and laterally overgrown regions on SiO2

The nature of the lattice defects in selective epitaxial (001) silicon in SiO2 windows and in laterally overgrown regions on SiO2 films were characterized using a transmission electron microscope. Stacking faults, the dominant defects in the windows with near {110} sidewalls, were eliminated in the films grown at temperatures lower than 850°C. Twinning, which was frequently observed in 〈110〉 laterally overgrown regions, was also suppressed by lowering the growth temperature, but occurred even at a growth temperature of 800°C. The generation of defects is discussed from the viewpoint of the stability of the Si/SiO2 interface. Twin formation in laterally overgrown regions at lower growth temperatures is considered to be the result of the growth direction change from vertical to lateral. The difference in defect nature, between SFs in vertically grown regions and twins in laterally overgrown regions, is explained by the defect structure at the initial stage of generation. Films overgrown on SiO2 along the 〈100〉 direction exhibit few defects in the temperature range of 800 to 950°C; however, dislocations and small voids are present in the region where two overgrowth fronts coalesce irrespective of the growth temperature. Typical dislocations are of screw-type, showing that they are not caused by stress relaxation.

Scaled CMOS technology using SEG isolation and buried well process

An advanced bulk CMOS technology has been developed using the selective epitaxial growth (SEG) isolation technique and buried n-well process. CMOS devices are fabricated on a selective epitaxial layer, isolated by a thick SiO2insulator over the p+substrate. p-channel devices are designed on buried n-wells, formed by introducing a phosphorus ion implantation into the p+substrate before the epitaxial growth. The use of an SiO2sidewall and square side direction is effective for defect-free selective epitaxy. The epitaxial autodoping effect from the p+substrate and the buried layer is estimated to be within less than 1 µm. A 20-nm-thick gate oxide and 500-nm-thick phosphorus-doped polysilicon gate electrode are used for both channel devices. Submicrometer gate CMOS operation is confirmed using the SEG isolation technique. This isolation structure, combined with the buried well, shows large latchup immunity for scaled CMOS circuits.