Ichiro Tamitani

A real-time video signal processor suitable for motion picture coding applications

A real-time video signal processor (VSP) system has been developed. The system employs three multiprocessor clusters, each of which has 12 video signal processor modules (VSPMs). A VSPM in a cluster processes its assigned subimage by using an overlap-save technique. Each cluster uses the same multiprocessor structure, in which homogeneous processor modules are connected to input, output, and feedback buses in parallel and two bus switch units. By controlling these units, the clusters can be combined in pipeline and/or parallel forms. Each cluster also uses a variable delay unit which achieves up to one frame delay on the feedback bus. By using this unit, interframe processing can be carried out without using internal data memories in VSPMs for the frame delay. The employment of the bus switches and the variable delay unit increases flexibility for a variety of signal processing algorithms. The system performs 500 million operations per second and is currently used as a real-time evaluation system for low-bit-rate picture encoders. >

A microprogrammable real-time video signal processor (VSP) for motion compensation

A video signal processor (VSP) LSI circuit with a three pipelined architecture has been developed for pattern matching, which is fundamental for the motion compensation necessary for teleconferencing systems. A high-speed arithmetic logic unit with absolute-value calculation capability and a minimum/maximum value detector, which are essential to pattern matching, have been integrated on the VSP LSI. The chip was fabricated with a 2.5- mu m CMOS and double-layer metallization technology. The number of MOSFETs integrated on the 9.91*9.50-mm/sup 2/ chip is about 48000. It operates at a 14.3-MHz clock frequency with a single 5-V power supply and typically consumes 240 mW. An experimental video signal processing system, using a single VSP LSI chip, is discussed. >

Hardware architecture for rapid generation of electro-holographic fringe patterns

This report describe the hardware architecture and software implementation of a hologram computing system developed at the MIT Media Laboratory. The hologram computing employs specialized stream-processing hardware embedded in the Cheops Image Processing system--a compact, block data-flow parallel processor. A superposition stream processor performs weighted summations of arbitrary 1D basis functions. A two-step holographic computation method--called Hogel-Vector encoding--utilizes the stream processors computational power. An array of encoded hogel vectors, generated from a 3D scene description, is rapidly decoded using the processor. The resulting 36-megabyte holographic pattern is transferred to frame- buffers and then fed to a real-time electro-holographic display, producing 3D holographic images. System performance is sufficient to generate an image volume approximately 100 mm per side in 3 seconds. The architecture is scalable over a limited range in both display size and computational power. The limitations on system scalability will be identified and solutions proposed.

Parallel video signal processor configuration based on overlap-save technique and its LSI processor element: VISP

A parallel signal processor architecture has been developed for real time motion picture encoding. The architecture is based on spatial parallelism utilization in a picture signal. Plural element processors handle subregional pictures simultaneously without communicating with other element processors. However, due to an overlapsave technique where every sub-picture input area is chosen to be wider than the output area, element processors can carry out continuous processing over an entire picture. In order to increase motion picture processing efficiency as well as system implementation simplicity, a specific element processor LSI chip, composed of a pipeline arithmetic unit, two dimensional address generators, a raster scan signal handler, and a sequence controller, has been developed by using more than 220,000 transistors. The developed parallel processor is shown to be applicable to a software programmable low bit rate TV codec.

A microprogrammable real-time video signal processor (VSP) LSI

A microprogrammable real-time video signal processor (VSP) LSI has been developed for constructing a parallel video signal processing system. The VSP LSI employs a flexible multistage pipelined architecture and can handle such sophisticated image signal processing as high-speed edge detection and motion compensation. It contains many operational function units such as an arithmetic logic unit and with absolute value calculation capability, a minimum/maximum value detector, a two-port SRAM, RAM address pointer and clocked bus lines. The VSP LSI has been designed using two different kinds of automatic layout programs. The chip, which was fabricated with a 2.5-/spl mu/m CMOS and double-layer metallization technology, has an area of 9.91/spl times/9.50 mm/SUP 2/ and contains about 48000 MOSFETs. It operates at a clock frequency of 14.3 MHz with a single 5-V power supply and typically consumes 240 mW. An experimental system, using a single VSP LSI chip, has been constructed in order to demonstrate various application capabilities, such as interframe difference operations, high-speed edge detection and motion compensation.

A real-time HDTV signal processor: HD-VSP

A programmable real-time high-definition television (HDTV) signal processor (HD-VSP) has been developed. For conventional TV signals, a previously reported video signal processor (VSP) has introduced flexible software control capability based on subregional processing. In order to expand such flexibility for real-time HDTV signal processing, the HD-VSP employs eight VSP clusters and programmable time-expansion/compression units. An input HDTV signal is converted to eight time-expanded subregional signals to reduce their sampling rate to that of conventional TV signals. The converted signals are then processed by the eight clusters in the same manner as the VSP. Therefore, programs developed for conventional TV signals can be applied to HDTV with little modification. Processed signals obtained from the eight clusters are time-compressed and multiplexed to reconstruct an output HDTV signal. This HD-VSP has 16 component processors per cluster and is capable of 2.5 giga-operations/s. Several coder programs, including a discrete cosine transform coder and an intraframe differential pulse code modulation (PCM) coder, are developed to evaluate HDTV coding efficiency. >

A real-time HDTV signal processor: HD-VSP-system and applications

A programmable real-time HDTV (high-definition television) video signal processor (HD-VSP) has been developed. The HD-VSP is composed of multiprocessor clusters. Each cluster is compatible with a previously reported VSP. The VSP has introduced flexible software control capability in conventional TV signal processing. In order to expand such flexibility for HDTV signals, the developed HD-VSP employs a signal conversion technique. The HDTV sampling rate is reduced to that of plural conventional TV signals, each of which can be processed by VSP parallel multiprocessor clusters. Therefore, programs developed for conventional TV signals on the VSP are also applied to HDTV signals by the new system. Several coder programs, including a discrete cosine transform coder and an intraframe differential PCM (pulse code modulation) coder, are developed to evaluate real-time HDTV coding efficiency.<<ETX>>