Hideyuki Ichihara

High-level synthesis for multi-cycle transient fault tolerant datapaths

As the advance in semiconductor technology, the tolerance for transient faults caused by particle strike, called SET (single event transient), becomes an important issue, and moreover future technologies bring the possibility of occurrence of long duration errors spanning across multiple cycles of the circuits due to particle strike. In this paper we discuss high-level synthesis for multi-cycle transient fault tolerant datapaths. Clarifying the conditions for multi-cycle error correctability and detectability of multi-cycle transient fault tolerant datapaths, we propose a heuristic algorithm for finding optimal operator binding of kc-cycle error correctable / kd-cycle error detectable datapaths with minimum operators. The method focuses on only transient faults (not permanent ones), and therefore it can derive appropriate designs necessary and sufficient for tolerance of SET avoiding use of excessive hardware resources.

Compact and accurate stochastic circuits with shared random number sources.

Stochastic computing, which is an approximate computation with probabilities (called stochastic numbers), draws attention as an alternative method of deterministic computing. In this paper, we discuss a design of compact and accurate stochastic circuits. Stochastic circuits are known as a way to stochastically compute complex calculation at low hardware cost, while stochastic number generators (SNGs), which are used for converting deterministic numbers into stochastic numbers, account for a large fraction of the circuits. To reduce such SNGs in stochastic circuits, we propose a technique to share random number generators with several SNGs. This sharing method employs circular shift of the output of LFSRs to reduce the correlation between stochastic numbers. We also discuss the influence of input correlation around a multiplexer, which is a scaled adder for stochastic computing, so as to avoid over reducing the input correlation. Application of the proposed techniques to two stochastic image processing shows the reduction in the size of SNGs without greatly sacrificing accuracy.

An FPGA-based fail-soft system with adaptive reconfiguration

Fail-soft systems with reconfigurable devices, which recover themselves by repeating isolation of faulty portions with graceful degradation, have been proposed [14]. In this paper, we proposed a fail-soft system on an FPGA and discuss the performance and availability of the system. The proposed system can infer the type of faults from obtained errors, and then adaptively reconfigure itself autonomously, so that it can achieve high availability while keeping high performance. Case studies show that the proposed system can achieve high availability with high performance by avoiding excessive recovery.

A Practical Approach to Threshold Test Generation for Error Tolerant Circuits

Threshold testing, which is an LSI testing method based on the acceptability of faults, is effective in yield enhancement of LSIs and selective hardening for LSI systems. In this paper, we propose test generation models for threshold test generation. Using the proposed models, we can efficiently identify acceptable faults and generate test patterns for unacceptable faults with a general test generation algorithm, i.e., without a test generation algorithm specialized for threshold testing. Experimental results show that our approach is practically effective.

Generating small test sets for test compression/decompression scheme using statistical coding

A test compression/decompression scheme using statistical coding is proposed for design-for-testability (DFT) in order to reduce test application cost. In this scheme, a given test set of a VLSI circuit is compressed by statistical coding beforehand, and then decompressed while the VLSI circuit is tested. Previously, we proposed a method for generating test sets suitable for the test compression scheme. The method generates a small compressed test set, although the number of test-patterns included in the test set is not always small. In this paper, we propose a method to generate highly compressible test sets while keeping the number of generated test sets small. Experimental results show that our method can generate small, compressible test sets in short computational time.

A Fast Threshold Test Generation Algorithm Based on 5-Valued Logic

Threshold testing, which is a VLSI testing method based on the acceptability of faults, is effective in yield enhancement of VLSIs and in selectively hardening VLSI systems. A test generation algorithm for generating test patterns for unacceptable faults has been proposed, which is based on the 16-valued logic system. In this paper, we propose a fast test generation algorithm based on the 5-valued logic system. Experimental results show that our proposed algorithm can generate test patterns for unacceptable faults with small computational time, compared with that based on the 16-valued logic system.

Reliability and Performance Analysis of FPGA-Based Fault Tolerant System

FPGAs are applicable to implementation of fault tolerant systems due to their reconfigurability. Such fault tolerant systems can be classified according to recovering methods: fail-soft and stand-by-redundant systems. In this work, we propose a probabilistic model for both FPGA-based fault tolerant systems, and analyze the reliability and performance of the systems. Analytical results show that there exists an appropriate choice of the implementation of fault tolerance with FPGAs between the two systems for the specification required for its application.

Compact and Accurate Digital Filters Based on Stochastic Computing

Stochastic computing (SC), which is an approximate computation with probabilities, has attracted attention as an alternative to deterministic computing. In this paper, we discuss a design method for compact and accurate digital filters based on SC. Such filter designs are widely used for various purposes, such as image and signal processing and machine learning. Our design method involves two techniques. One is sharing random number sources with several stochastic number generators to reduce the areas required by these generators. Clarifying the influence of the correlation around multiplexers (MUXs) on computation accuracy and utilizing circular shifts of the output of random number sources, we can reduce the number of random number sources for a digital filter without losing accuracy. The other technique is to construct a MUX tree, which is the principal part of an SC-based filter. We formulate the correlation-induced errors produced by the MUX tree, and then propose an algorithm for constructing an optimum MUX tree to minimize the error. Experimental results show that the proposed design method can derive compact (approximately 70 percent area reduction) SC-based filters that retain high accuracy.

Scheduling algorithm in datapath synthesis for long duration transient fault tolerance

As the advance in semiconductor technologies, transient faults caused by particle strike in combinational logic, so-called SETs, have become a matter of concern, and further it is predicted that such faults can span across more than one clock cycle. This paper presents a scheduling algorithm in high-level synthesis of long duration transient fault tolerant datapaths. On the basis of the properties of operational units for error correction and detection in behaviorally tripled module systems, we introduce the concept of forces among operations in unscheduled data-flow graphs, and propose a scheduling algorithm based on well-known force-directed scheduling. Experimental results show that the proposed scheduling algorithm can derive multi-cycle fault tolerant datapaths with small hardware resources compared with simply-tripled datapaths.

A Self-Test of Dynamically Reconfigurable Processors with Test Frames

This paper proposes a self-test method of coarse grain dynamically reconfigurable processors (DRPs) without hardware overhead. In the method, processor elements (PEs) compose a test frame, which consists of test pattern generators (TPGs), processor elements under test (PEUTs) and response analyzers (RAs), while testing themselves one another by changing test frames appropriately. We design several test frames with different structures, and discuss the relationship of the structures to the numbers of contexts and test frames for testing all the functions of PEs. A case study shows that there exists an optimal test frame which minimizes the test application time under a constraint.