Toshimasa Kuchii

On configuring scan trees to reduce scan shifts based on a circuit structure

In this paper, a new method for reducing test application time of sequential circuits with scan design is proposed. Scan design is one of most popular design for testability techniques. To reduce scan shifts required to provide the scan pattern, a fully testable scan tree configuration is proposed. The method can configure scan trees before generating test vectors without degrading fault coverage by considering a circuit structure. In a fully testable scan tree, flip-flops are placed in parallel in case that they have no overlap in the set of the outputs connected from them. To reduce much scan shifts, a folding scan tree, which is configured based on a fully testable scan tree by placing more flip-flops in parallel, is also configured. Moreover, a scan tree configuration considering scan-out operation is also presented. Experimental results for benchmark circuits are shown.

Supply current test for unit-to-unit variations of electrical characteristics in gates

A practical supply current test method is proposed and the experimental evaluation results are presented. In the method, the unit-to-unit variation of electrical characteristics in each logic gate is modeled as a Gaussian distribution and faults are detected with a statistical hypothesis technique.

Algorithmic test generation for supply current testing of TTL combinational circuits

In this paper, an algorithmic test generation method for supply current testing of TTL combinational circuits is proposed. In this method, primary input assignment like in PODEM is used for sensitizing a fault and generating the fault effect on supply current of a circuit under test. Test input vectors for ISCAS-85 benchmark circuits are derived by a random method and the proposed algorithmic method. The test generation results show that with the algorithmic method, test input vectors of faults, whose test vectors can not be derived with the random method, can be derived.

Test input generation for supply current testing of bridging faults in bipolar combinational logic circuits

A test input generation algorithm for supply current tests is proposed to detect bridging faults in bipolar combinational circuits. By using the algorithm, test input vectors are derived for ISCAS-85 benchmark circuits, which are implemented on printed boards. It is shown by the test generation that more faults in bipolar circuits can be detected with a smaller number of test input vectors than a conventional test method based on output logic values.