Hideyuki Matsuoka

2Mb Spin-Transfer Torque RAM (SPRAM) with Bit-by-Bit Bidirectional Current Write and Parallelizing-Direction Current Read

A 1.8V 2Mb spin-transfer torque RAM chip using a 0.2mum logic process with an MgO tunneling barrier cell demonstrates the circuit technologies for potential low-power non-volatile RAM, or universal memory. This chip features an array scheme with bit-by-bit bidirectional current write to achieve proper spin-transfer torque writing in 100ns, and parallelizing-direction current reading with a low-voltage bit-line that leads to 40ns access time.

A multi-level-cell spin-transfer torque memory with series-stacked magnetotunnel junctions

We first report a multi-level-cell (MLC) spin-transfer torque memory (SPRAM) with series-connected magnetotunnel junctions (MTJs). The series MTJs (with different areas) show multi-level resistances by a combination of their magnetization directions. A four-level operation by spin-transfer-torque writing was experimentally demonstrated. A scheme for the write/read operation of the MLC SPRAM was also presented.

Current-Induced Magnetization Switching in MgO Barrier Magnetic Tunnel Junctions With CoFeB-Based Synthetic Ferrimagnetic Free Layers

We investigated the effect of using a synthetic ferrimagnetic (SyF) free layer in MgO-based magnetic tunnel junctions (MTJs) on current-induced magnetization switching (CIMS), particularly for application to spin-transfer torque random access memory (SPRAM). The employed SyF free layer had a Co₄₀Fe₄₀B₂₀/Ru/Co₄₀Fe₄₀B₂₀and Co₂₀Fe₆₀B₂₀/Ru/Co₂₀Fe₆₀B₂₀structures, and the MTJs (100 times (150-300) nm²) were annealed at 300 ^degC. The use of SyF free layer resulted in low intrinsic critical current density (<i>J</i> _c0) without degrading the thermal-stability factor (<i>E</i>/<i>k</i> _B <i>T</i>, where <i>E</i>, <i>k</i> _B, and <i>T</i> are the energy potential, the Boltzmann constant, and temperature, respectively). When the two CoFeB layers of a strongly antiferromagnetically coupled SyF free layer had the same thickness, <i>J</i> _c0 was reduced to 2-4 times10⁶ A/cm². This low <i>J</i> _c0 may be due to the decreased effective volume under the large spin accumulation at the CoFeB/Ru. The <i>E</i>/<i>k</i> _B <i>T</i> was over 60, resulting in a retention time of over ten years and suppression of the write current dispersion for SPRAM. The use of the SyF free layer also resulted in a bistable (parallel/antiparallel) magnetization configuration at zero field, enabling the realization of CIMS without the need to apply external fields to compensate for the offset field.

Coulomb blockade in the inversion layer of a Si metal‐oxide‐semiconductor field‐effect transistor with a dual‐gate structure

We have studied the transport properties of artificially squeezable inversion layers in a Si metal‐oxide‐semiconductor field‐effect‐transistor with a dual‐gate structure. Increasing the potential barrier height with constant intervals along the one‐dimensional channel gradually transforms a simple quantum wire into coupled quantum dots. The clear change in transport properties has been observed by changing the tunnel barrier height at low temperatures. The experimental results are discussed in terms of one‐dimensional subbands and the Coulomb blockade of single‐electron tunneling.

A GeSbTe phase-change memory cell featuring a tungsten heater electrode for low-power, highly stable, and short-read-cycle operations

This paper presents a GeSbTe memory cell with a tungsten heater electrode. The cell has the lowest reset current (50 /spl mu/A) ever reported for a phase-change memory device. The factors responsible for re-amorphization, which increased the instability of crystallization are shown. The GeSbTe cell in this work offers a read-time within 2 nsec, which allows 200 MHz-chip operation with negligible effects of read disturbance.

A disturbance-free read scheme and a compact stochastic-spin-dynamics-based MTJ circuit model for Gb-scale SPRAM

A magnetic-tunnel-junction (MTJ) circuit model, which considers spin dynamics under finite temperature, electrical bias, a stochastic process, and spin-transfer torque, was developed. Switching behaviors simulated by this model were verified by experimental measurements. Moreover, a disturbance-free read scheme for Gbit-scale spin-transfer torque RAM (SPRAM) was also developed. The feasibility of this scheme was confirmed by circuit simulation using the model and on-chip measurement of switching probability.

A novel SPRAM (SPin-transfer torque RAM) with a synthetic ferrimagnetic free layer for higher immunity to read disturbance and reducing write-current dispersion

A novel SPRAM (spin-transfer torque RAM) consisting of MgO-barrier-based magnetic tunnel junctions (MTJs) with a synthetic ferrimagnetic (SyF) structure in a free layer was demonstrated for both higher immunity to read disturbance and a sufficient margin between the read and write currents. Since magnetization of the free layer becomes stable against thermal fluctuation with increasing thermal-stability factor E/kBT, the SyF free layer of the MTJs realized a magnetic information retention of over 10 years due to its high E/kBT of 67. Furthermore, it was found that the SyF free layer has an advantage of reducing dispersion of write-current density Jc, which is necessary for securing an adequate margin between the read and write currents.

Dependence of Magnetic Anisotropy in Co20Fe60B20 Free Layers on Capping Layers in MgO-Based Magnetic Tunnel Junctions with In-Plane Easy Axis

Perpendicular magnetic anisotropy (PMA) in Co20Fe60B20 films depending on the adjacent layers of Ta, Ru, and MgO was studied for reduction of switching current density Jc0 in in-plane magnetic tunnel junctions (MTJs). A MgO layer reduces the out-of-plane saturation field (Hs) of in-plane easy axis Co20Fe60B20 films by inducing a strong PMA at the Co20Fe60B20/MgO interface. The PMA is not affected much by the crystallinity in Co20Fe60B20 films with different capping layers. MTJ with a MgO capping layer shows a lower Jc0 than that with a Ru capping layer, in accordance with the reduction of Hs.

Transport properties of a silicon single‐electron transistor at 4.2 K

We report on the transport properties of a silicon single‐electron transistor at 4.2 K. A quantum dot is formed in the inversion layer of a silicon metal‐oxide‐semiconductor field‐effect transistor with a dual‐gate structure by introducing controllable tunnel barriers in the narrow channel. Periodic current oscillations due to the single‐electron charging effect have been observed. Furthermore, current in the Coulomb blackade regime is explained by the inelastic cotunneling theory at finite temperatures.

2Mb SPRAM Design: Bi-Directional Current Write and Parallelizing-Direction Current Read Schemes Based on Spin-Transfer Torque Switching

A 1.8 V 2-Mb SPRAM (SPin-transfer torque RAM) chip using 0.2-mum logic process with MgO tunneling barrier cell demonstrates the circuit technologies for potential low power non-volatile RAM, or universal memory. This chip features: an array scheme with bit-by-bit bi-directional current write to achieve proper spin-transfer torque writing of 100-ns, and parallelizing-direction current reading with low voltage bit-line that leads to 40-ns access time.