Takeshi Sakata

Switched-source-impedance CMOS circuit for low standby subthreshold current giga-scale LSI's

A switched-source-impedance (SSI) CMOS circuit is proposed as a means of reducing the exponential increase of subthreshold current with threshold-voltage scaling. Inserting a switched impedance at the source of a MOS transistor reduces the standby subthreshold current of giga-scale LSIs operating at room temperature by three to four orders of magnitude and suppresses the current variation caused by threshold-voltage and temperature fluctuations. The scheme is applicable to any combinational and sequential CMOS logic circuits as long as their standby node voltages are predictable. The standby current of a 16-Gb DRAM is expected to be reduced from 1.1 A to 0.29 mA using this scheme. Hence, battery backup of giga-scale LSIs will be possible even at room temperature and above. >

Subthreshold-current reduction circuits for multi-gigabit DRAM's

Two subthreshold-current reduction circuit schemes are described to suppress the increase in current in multi-gigabit DRAMs. One is a hierarchical power-line scheme for iterative circuits. In this scheme, a group of circuits is divided into blocks; only the selected block is supplied with power, while the subthreshold current to the many nonselected blocks is reduced. This scheme minimizes the number of circuits carrying the large subthreshold current. Applications of this scheme to word drivers, decoders and sense-amplifier driving circuits are shown. The other scheme is a switched-power-supply inverter with a level holder for random combinational logic circuits. In the active mode of the chip, the operating period of the inverter is distinguished from the inactive period. The inverter is supplied with power only in the operating period, while in the inactive period the subthreshold current is shut off and the output level is kept by the flip-flop level holder. This scheme shortens the period in which the large subthreshold current flows. Both schemes are evaluated for a conceptually-designed 16-Gb DRAM. They reduce its active current by ten-fold from the conventional 1.2 A to 116 mA. >

A precise on-chip voltage generator for a gigascale DRAM with a negative word-line scheme

A precise on-chip voltage generator for gigascale DRAMs with a negative word-line scheme is described. It combines a charge-pump regulator and a series-pass regulator, and it also includes a positive and negative offset voltage generator that uses a bandgap generator with a differential amplifier. The proposed circuit was experimentally evaluated with a test device fabricated using a 0.3-/spl mu/m process. The simulation results show that the series-pass regulator suppresses the noise on a word-line low voltage (negative) to below 30 mV for the word-line transient and V/sub BB/ bouncing. A dc-voltage error of less than 6% without trimming is confirmed for the positive and negative offset voltage generator through the test device. These results show that the described scheme can be used in future low-voltage gigascale DRAMs.

Two-dimensional power-line selection scheme for low subthreshold-current multi-gigabit DRAM's

Two-dimensional power-line selection scheme for an iterative CMOS circuit block, is proposed to reduce the subthreshold current. In this scheme, a block is divided into sub-blocks of two-dimensional arrangement and selectively energized by two-dimensional power-line selection. The scheme combined with dual word-line structure permits a drastic active current reduction to one sixteenth, from 363 mA to 22 mA, for a 16-Gb DRAM.

A single 1.5-V digital chip for a 10/sup 6/ synapse neural network

A digital-chip architecture for a 10(6)-synapse neural network is proposed. It runs on a 1.5-V dry cell to allow its use in portable equipment. An on-chip DRAM cell array stores synapse weights digitally to provide easy programmability and automatic refreshing. A pitch-matched interconnection and a combinational unit circuit for summing product allow a tight layout. A dynamic data transfer circuit and the 1.5-V operation of the entire chip reduce the power dissipation, but the parallel processing nonetheless provides high speed at the 1.5-V supply. Estimated power dissipation of 75 mW and a processing speed of 1.37 giga connections per second are predicted for the chip. The memory and the processing circuits can be integrated on a 15.4-mmx18.6-mm chip by using a 0.5-mum CMOS design rule. A scaled-down version of the chip that has an 8-kb DRAM cell array was fabricated, and its operation was confirmed.

An experimental 220-MHz 1-Gb DRAM with a distributed-column-control architecture

A distributed-column-control architecture is proposed to reduce the burst-mode cycle time of large-capacity DRAMs. It features independent operation of the I/O block and subarrays, eliminating the wiring delay in the internal buses from the longest pipeline stage. The timing difference between the I/O block and the subarrays is compensated for by event-driven circuits. This architecture also eliminates the timing margin between the activation of column selection lines, reducing the cycle time by 25%. To evaluate this architecture, an experimental synchronously operating 1-Gb DRAM was designed and fabricated using a 0.16-/spl mu/m CMOS process. It operates with a 22O-MHz clock and a 1.5-V power supply.

Low-noise, high-speed data transmission using a ringing-canceling output buffer

The proposed ringing-canceling output buffer transmits a superimposed two-step pulse that almost completely cancels the ringing in the received waveform. Simulation showed that this circuit increases the noise margin by a factor of 2.6 compared to using a conventional circuit in a bus interface at a data rate of 200 MHz. A test circuit was designed and fabricated to experimentally verify the fundamental ringing-canceling effect. Compared with other approaches to reducing ringing, the ringing-canceling output buffer provides a bigger improvement in the noise margin with a smaller signal-delay. This output buffer is promising for improving the data transfer rate of the memory bus.

Reviews and prospects of high-density RAM technology

We review memory-chip and memory-cell developments of various VLSI memories over the last three decades, trends in DRAM technology (such as power-supply schemes and gate oxide thickness compared with those of MPUs, memory-cell structures and multi-divided arrays for modern DRAMs), state-of-the art embedded DRAM technology for high-speed, low-cost and low-voltage designs, and prospects for emerging RAMs such as FeRAMs and MRAMs.

A dynamic CAM - based on a one-hot-spot block code - for millions-entry lookup

With the aim of realizing large-scale and low-power CAMs for millions-entry lookup, the authors have devised a one-hot-spot block code and developed three circuit techniques. The proposed code efficiently stores IP addresses and reduces the entry count down by 52% on average. The first and second techniques, a hierarchical match-line structure and an on-chip entry compression/extraction scheme, enable the proposed code to be applied to our new CAM. In addition to the second technique, the third technique, a search-depth control scheme, restricts activating unneeded search lines and reduces power consumption down by 45%. In the case of 72-bit data, the proposed CAM, using a stacked capacitor, effectively achieves 1.5 million entries, which is six times larger than that of a conventional static TCAM.

The charge-share modified (CSM) precharge-level architecture for high-speed and low-power ferroelectric memory

A charge-share modified (CSM) precharge-level architecture for selective subdataline activation designed to simultaneously achieve high-speed and low-power ferroelectric nonvolatile memories is described. In this architecture, to read the data of only one memory cell destructively, the precharge level of the selected subdataline is modified by charge-sharing between the subdataline and main dataline. This architecture enables high-speed read operations, because the operations of modifying the precharge level and reading the data of memory cells are achieved simultaneously. Three circuit technologies are used in the CSM architecture to increase the operating margin: self-timing precharge circuits which solve the polarization disturbance problem without adding extra signal lines or timing margins, a boosted precharge level technique which increases the signal voltage of the nonvolatile data, and shared dummy cell circuits which improve the precision of the reference voltage over that of a conventional voltage generator. These techniques and circuits are evaluated for a simulated 16-Mb ferroelectric memory. They reduce the access time by 20 ns to 51 ns compared with the conventional architecture, while reducing the memory array current to less than 1% that of the all-subdataline activation technology.