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Dive into the research topics where Hieu Van Tran is active.

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Featured researches published by Hieu Van Tran.


Archive | 2018

Split-Gate Floating Poly SuperFlash ® Memory Technology, Design, and Reliability

Nhan Do; Hieu Van Tran; Alex Kotov; Vipin Tiwari

Split-gate embedded flash memory technology has been around for a couple of decades and has become a de facto standard for embedded products such as microcontrollers and smart cards. The majority of the large microcontroller and smartcard chip-makers and a series of fabless companies are now using some form of a split-gate embedded flash-memory technology because of its advantages in power, performance, and cost compared with traditional EEPROM or stacked-gate solutions. This chapter covers the fundamentals of split-gate embedded flash memories with an emphasis on SST’s widely adopted SuperFlash® memory technology as an example to demonstrate the benefits of a split-gate embedded flash-memory technologies. The fundamentals of SuperFlash technology, design, reliability, and scalability are discussed in detail in various sections, which would provide a detailed understanding of a split-gate, embedded flash-memory technology.


european solid-state circuits conference | 2005

A precision high voltage wave-shaper for multi-Gbit source side injection MLC NOR flash memory

Hieu Van Tran; William John Saiki; Jack Edward Frayer; Thuan Vu; Anh Ly; Sang Thanh Nguyen; Hung Quoc Nguyen; Douglas Lee; Michael Stephen Briner

A precision high voltage wave-shaper is demonstrated in 0.18/spl mu/m 64-256Meg NOR SSI flash MLC memory chip to demonstrate feasibility of a /spl sim/8bit accuracy HV delivering system for 1.8V multi giga bit (>4 Gbit) density 4bits/cell multilevel memory. Dynamic adaptive HV bias scheme (DYAHV) and unique nested array driving loop shown for the first time in this work.


Archive | 2002

High voltage generation and regulation system for digital multilevel nonvolatile memory

William John Saiki; Hieu Van Tran; Sakhawat M. Khan


Archive | 2001

Array architecture and operating methods for digital multilevel nonvolatile memory integrated circuit system

Hieu Van Tran; Sakhawat M. Khan; George J. Korsh


Archive | 2002

Multistage autozero sensing for a multilevel non-volatile memory integrated circuit system

Hieu Van Tran


Archive | 2000

Testing of multilevel semiconductor memory

George J. Korsh; Sakhawat M. Khan; Hieu Van Tran


Archive | 2002

Digital multilevel memory system having multistage autozero sensing

Hieu Van Tran


Archive | 2003

Digital multilevel non-volatile memory system

Hieu Van Tran


Archive | 2007

Wide dynamic range and high speed voltage mode sensing for a multilevel digital non-volatile memory

Hieu Van Tran; Sakhawat M. Khan


Archive | 1996

Method and apparatus for analog reading values stored in floating gate structures

Hieu Van Tran; James Brennan; Trevor Blyth; Sukyoon Yoon

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Anh Ly

Microchip Technology

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Thuan Vu

Microchip Technology

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Nhan Do

Microchip Technology

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